Apparatus and method for integrated circuit design with improved delay variation calculation based on power supply variations
First Claim
1. An integrated circuit design apparatus comprising:
- a power supply voltage variation analysis tool calculating variations of power supply voltages of respective instances integrated within a target circuit;
a determination module comparing said variations of said power supply voltages with first and second reference levels, said second reference level being smaller than said first reference level;
a redesign module adapted to redesign said target circuit when at least one of said variations of said power supply voltages is larger than said first reference level;
a delay variation calculation module adapted to correct circuit delay data of said respective instances based on said variations of said power supply voltages of said respective instances; and
a static timing analysis tool performing timing verification of said target integrated circuit,wherein, in said timing verification, said corrected circuit delay data are used for a specific instance out of said instances within said target circuit, when a variation of a power supply voltage of said specific instance is in a range from said second reference level to said first reference level, and said circuit delay data uncorrected are used for said specific instance, when said variation of said power supply voltage of said specific instance is smaller than said second reference level.
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Abstract
An integrated circuit design apparatus is provided with a power supply voltage variation analysis tool calculating variations of power supply voltages of respective instances integrated within a target circuit; a determination module comparing the variations of the power supply voltages with first and second reference levels, the second reference level being smaller than the first reference level; a redesign module adapted to redesign the target circuit when at least one of the variations of the power supply voltages is larger than the first reference level; a delay variation calculation module adapted to correct circuit delay data of the respective instances based on the variations of the power supply voltages of the respective instances; a static timing analysis tool performing timing verification of the target integrated circuit. The timing verification in connection with each of the instances is performed based on the corrected circuit delay data, when a variation of a power supply voltage of the each of the instances is in a range from the second reference level to the first reference level, and performed based on the circuit delay data uncorrected, when the variation of the power supply voltage of the each of the instances is smaller than the second reference level.
19 Citations
19 Claims
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1. An integrated circuit design apparatus comprising:
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a power supply voltage variation analysis tool calculating variations of power supply voltages of respective instances integrated within a target circuit; a determination module comparing said variations of said power supply voltages with first and second reference levels, said second reference level being smaller than said first reference level; a redesign module adapted to redesign said target circuit when at least one of said variations of said power supply voltages is larger than said first reference level; a delay variation calculation module adapted to correct circuit delay data of said respective instances based on said variations of said power supply voltages of said respective instances; and a static timing analysis tool performing timing verification of said target integrated circuit, wherein, in said timing verification, said corrected circuit delay data are used for a specific instance out of said instances within said target circuit, when a variation of a power supply voltage of said specific instance is in a range from said second reference level to said first reference level, and said circuit delay data uncorrected are used for said specific instance, when said variation of said power supply voltage of said specific instance is smaller than said second reference level. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A computer-readable recording medium which records a program that when executed controls a computer to perform a method comprising:
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calculating variations of power supply voltages of respective instances integrated within a target circuit; comparing said variations of said power supply voltages with first and second reference levels, said second reference level being smaller than said first reference level; redesigning said target circuit when at least one of said variations of said power supply voltages is larger than said first reference level; correcting circuit delay data of each of said respective instances based on a variation of a power supply voltage of said each of said respective instances, when said variation of said power supply voltage of said each of said instances is in a range from said second reference level to said first reference level; and performing timing verification of said target circuit, wherein, in said timing verification, said corrected circuit delay data are used for a specific instance out of said instances within said target circuit, when a variation of a power supply voltage of said specific instance is in a range from said second reference level to said first reference level, and said circuit delay data uncorrected are used for said specific instance, when said variation of said power supply voltage of said specific instance is smaller than said second reference level. - View Dependent Claims (11, 12, 13, 14)
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15. An integrated circuit design method comprising:
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calculating variations of power supply voltages of respective instances integrated within a target circuit; comparing said variations of said power supply voltages with first and second reference levels, said second reference level being smaller than said first reference level; redesigning said target circuit when at least one of said variations of said power supply voltages is larger than said first reference level; correcting circuit delay data of each of said respective instances based on a variation of a power supply voltage of said each of said respective instances, when said variation of said power supply voltage of said each of said instances is in a range from said second reference level to said first reference level; and performing timing verification of said target circuit, wherein, in said timing verification, said corrected circuit delay data are used for a specific instance out of said instances within said target circuit, when a variation of a power supply voltage of said specific instance is in a range from said second reference level to said first reference level, and said circuit delay data uncorrected are used for said specific instance, when said variation of said power supply voltage of said specific instance is smaller than said second reference level. - View Dependent Claims (16, 17, 18, 19)
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Specification