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VARIOUS METHODS AND APPARATUS TO SUPPORT OUTSTANDING REQUESTS TO MULTIPLE TARGETS WHILE MAINTAINING TRANSACTION ORDERING

  • US 20080320476A1
  • Filed: 06/24/2008
  • Published: 12/25/2008
  • Est. Priority Date: 06/25/2007
  • Status: Active Grant
First Claim
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1. An interconnect for an integrated circuit to communicate transactions between one or more initiator Intellectual Property (IP) cores and multiple target IP cores coupled to the interconnect, wherein the interconnect implements logic configured to support multiple transactions issued from a first initiator IP core to the multiple target IP cores while maintaining an expected execution order within the transactions, wherein the logic supports a second transaction to be issued from the first initiator IP core to a second target IP core before a first transaction issued from the same first initiator IP core to a first target IP core has completed while ensuring that the first transaction completes before the second transaction, where the logic does not include any reorder buffering, and while ensuring an expected execution order within the first transaction and second transaction are maintained.

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