VARIOUS METHODS AND APPARATUS TO SUPPORT OUTSTANDING REQUESTS TO MULTIPLE TARGETS WHILE MAINTAINING TRANSACTION ORDERING
First Claim
1. An interconnect for an integrated circuit to communicate transactions between one or more initiator Intellectual Property (IP) cores and multiple target IP cores coupled to the interconnect, wherein the interconnect implements logic configured to support multiple transactions issued from a first initiator IP core to the multiple target IP cores while maintaining an expected execution order within the transactions, wherein the logic supports a second transaction to be issued from the first initiator IP core to a second target IP core before a first transaction issued from the same first initiator IP core to a first target IP core has completed while ensuring that the first transaction completes before the second transaction, where the logic does not include any reorder buffering, and while ensuring an expected execution order within the first transaction and second transaction are maintained.
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Accused Products
Abstract
A method, apparatus, and system are described, which generally relate to an integrated circuit having an interconnect that implements internal controls. The interconnect in an integrated circuit communicates transactions between initiator Intellectual Property (IP) cores and target IP cores coupled to the interconnect. The interconnect implements logic configured to support multiple transactions issued from a first initiator IP core to the multiple target IP cores while maintaining an expected execution order within the transactions. The logic supports a second transaction to be issued from the first initiator IP core to a second target IP core before a first transaction issued from the same first initiator IP core to a first target IP core has completed while ensuring that the first transaction completes before the second transaction and while ensuring an expected execution order within the first transaction and second transaction are maintained. The logic does not include any reorder buffering.
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Citations
20 Claims
- 1. An interconnect for an integrated circuit to communicate transactions between one or more initiator Intellectual Property (IP) cores and multiple target IP cores coupled to the interconnect, wherein the interconnect implements logic configured to support multiple transactions issued from a first initiator IP core to the multiple target IP cores while maintaining an expected execution order within the transactions, wherein the logic supports a second transaction to be issued from the first initiator IP core to a second target IP core before a first transaction issued from the same first initiator IP core to a first target IP core has completed while ensuring that the first transaction completes before the second transaction, where the logic does not include any reorder buffering, and while ensuring an expected execution order within the first transaction and second transaction are maintained.
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14. A method, comprising:
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maintaining an expected execution order of a set of transactions in a thread that are issued by an initiator Intellectual Property core across an interconnect to a target Intellectual Property core by use of flow control logic in a thread splitter unit internal to the interconnect that allows multiple requests from a given thread to be outstanding at any given time but restricts an issuance of a subsequent request from that thread having a destination address down a separate physical pathway from all of the outstanding requests in that thread; establishing a local order of received requests at the thread splitter unit; and maintaining the local order of requests in the thread to compare requests to other requests in that same thread to ensure the subsequent request to the separate physical pathway is not released from the thread splitter unit until all earlier requests from that same thread going to an initial physical pathway have communicated acknowledge signals back to the thread splitter unit. - View Dependent Claims (15, 16, 17, 18)
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19. An Integrated Circuit, comprising:
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multiple initiator IP cores; multiple target IP cores including memory IP cores; an interconnect to communicate requests as well as responses to those requests between the multiple initiator IP cores and the multiple target IP cores coupled to the interconnect; and flow logic internal to the interconnect to maintain an expected execution order of a set of transactions in a thread that are issued by a first initiator IP core across the interconnect to a first target IP core, wherein the flow control logic allows multiple requests from a given thread to be outstanding at any given time but restricts an issuance of a subsequent request from that thread having a destination address down a separate physical pathway from all of the outstanding requests in that thread. - View Dependent Claims (20)
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Specification