SEMICONDUCTOR DEVICE HAVING FLOATING BODY ELEMENT AND BULK BODY ELEMENT AND METHOD OF MANUFACTURING THE SAME

• US 20090001503A1
• Filed: 06/25/2008
• Published: 01/01/2009
• Est. Priority Date: 06/28/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Dong-Gun, Oh, Chang-Woo
• Granted Patent: US 8,178,924 B2
• Time in Patent Office: Days
• US Class Current: 257/506
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device having a floating body element and a bulk body element and a manufacturing method thereof are provided. The semiconductor device includes a substrate having a bulk body element region and floating body element regions. An isolation region defining an active region of the bulk body element region of the substrate and defining first buried patterns and first active patterns, which are sequentially stacked on a first element region of the floating body element regions of the substrate is provided. A first buried dielectric layer interposed between the first buried patterns and the substrate and between the first buried patterns and the first active patterns is provided.

Claims

1. A semiconductor device comprising:

a substrate including a bulk body element region and a floating body element region;

an isolation region defining an active region of the bulk body element region of the substrate and defining first buried patterns and first active patterns, which are sequentially stacked on a first element region of the floating body element region of the substrate; and

a first buried dielectric layer between the first buried patterns and the substrate and between the first buried patterns and the first active patterns.

2. The device of claim 1, wherein the first active patterns are self-aligned to the first buried patterns.

3. The device of claim 1, further comprising at least one first connection that connects the first buried patterns to each other, wherein the first connection is at a level of the first buried patterns or is spaced apart from sidewalls of the first active patterns by a thickness of a first buried dielectric layer covering the sidewalls.

4. The device of claim 1, wherein the first buried patterns comprise an n-type doped semiconductor layer, a p-type doped semiconductor layer, an undoped semiconductor layer and/or a metal layer.

5. The device of claim 1, wherein the plurality of first active patterns are on each of the first buried patterns.

6. The device of claim 3, further comprising:

second buried patterns and second active patterns, sequentially stacked on a second element region of the floating body element regions of the substrate and defined by the isolation region;

a second buried dielectric layer between the second buried patterns and the substrate and between the second buried patterns and the second active patterns; and

at least one second connection that connects the second buried patterns to each other and is a level of the second buried patterns.

7. The device of claim 6, wherein the second active patterns comprise thicknesses that are different than the first active patterns.

8. The device of claim 6, wherein the second buried patterns comprise thicknesses that are different than the first buried patterns.

9. The device of claim 6, wherein the second buried patterns comprise a material layer having characteristics that are different from the first buried patterns.

10. The device of claim 1, further comprising:

first lower gate contact structures electrically connected to each of the first buried patterns; and

a second lower gate contact structure electrically connected to the second buried patterns.

11. The device of claim 3, further comprising:

third buried patterns and third active patterns, sequentially stacked on a third element region of the floating body element regions of the substrate and defined by the isolation region;

at least one third connection that connects the third buried patterns to each other and covers sidewalls of the third active patterns; and

a third buried dielectric layer between the third buried patterns and the substrate, between the third buried patterns and the third active patterns, between the third connection and the substrate and between the third connection and the third active patterns.

12. The device of claim 1, further comprising:

a passivation layer on the substrate; and

an integrated circuit substrate on the passivation layer.

13. A semiconductor device comprising:

buried patterns on a substrate;

at least one connection extending from the buried patterns and connecting the buried patterns to each other;

active patterns on the buried patterns;

a buried dielectric layer between the buried patterns and the substrate, between the buried patterns and the active patterns, between the at least one connection and the substrate and between the at least one connection and the active patterns; and

at least one gate structure directly on the active patterns.

14. The device of claim 13, wherein the at least one connection is at a level of the buried patterns or covers sidewalls of the active patterns.

15. The device of claim 13, wherein the buried patterns are self-aligned to the active patterns.

16. The device of claim 13, wherein the plurality of active patterns are on each of the buried patterns.

17. The device of claim 13, wherein the active patterns comprises thicknesses that are different from each other.

18. The device of claim 13, wherein the buried patterns comprise thicknesses that are different from each other.

19. The device of claim 13, wherein the gate structure covers the sidewalls of the active patterns.

20. The device of claim 13, further comprising a lower gate contact structure electrically connected to the buried patterns.

21. A method of manufacturing a semiconductor device, comprising:

preparing a substrate having a bulk body element region and floating body element regions;

forming an isolation region defining an active region of the bulk body element region of the substrate, and defining first sacrificial patterns and first active patterns, which are sequentially stacked on a first element region of the floating body element regions of the substrate;

forming a first recessed region partially exposing the first sacrificial patterns in the isolation region using a photolithography and etching process;

removing the first sacrificial patterns to form first empty spaces below the first active patterns;

forming a first buried dielectric layer on an inner wall of the first empty space and an inner wall of the first recessed region; and

forming first buried patterns filling at least the first empty spaces on the substrate having the first buried dielectric layer.

22. The method of claim 21, further comprising:

defining second sacrificial patterns and second active patterns, which are sequentially stacked on a second element region of the floating body regions of the substrate, while the isolation region is formed, wherein the second active patterns have a different thickness from the first active patterns;

forming a second recessed region partially exposing the second sacrificial patterns in the isolation region;

removing the second sacrificial patterns to form second empty spaces below the second active patterns;

forming a second buried dielectric layer on an inner wall of the second empty space and an inner wall of the second recessed region; and

forming second buried patterns filling the second empty space.

23. A method of manufacturing a semiconductor device, comprising:

forming a sacrificial layer and an active layer, which are sequentially stacked, on a substrate;

patterning the sacrificial layer and the active layer to form sacrificial patterns and active patterns, which are sequentially stacked;

forming an isolation region surrounding the sacrificial patterns and the active patterns, which are sequentially stacked;

forming a recessed region in the isolation region to partially expose a sidewall of each of the sacrificial patterns;

selectively removing the sacrificial patterns to form empty spaces below the active patterns;

forming a buried dielectric layer on an inner wall of the empty spaces and an inner wall of the recessed region;

forming a buried layer filling the empty spaces and the recessed region on the substrate having the buried dielectric layer;

partially etching the buried layer to form buried patterns remaining in the empty spaces and a connection remaining in the recessed region to connect the buried patterns to each other; and

forming at least one gate structure on the active patterns.

24. The method of claim 23, wherein the active patterns have different thicknesses from each other.

25. A method of manufacturing a semiconductor device, comprising:

forming a sacrificial layer and an active layer, which are sequentially stacked, on a substrate;

patterning the sacrificial layer and the active layer to form sacrificial patterns and preliminary active patterns, which are sequentially stacked;

forming an isolation region surrounding the sacrificial patterns and the preliminary active patterns, which are sequentially stacked;

forming a recessed region in the isolation region to partially expose a sidewall of each of the sacrificial patterns;

selectively removing the sacrificial patterns having the exposed sidewall to form empty spaces below the preliminary active patterns;

forming a buried dielectric layer on an inner wall of the empty spaces and an inner wall of the recessed region;

forming buried patterns filling the empty spaces on the substrate having the buried dielectric layer;

patterning the preliminary active patterns to form a plurality of active patterns on each of the buried patterns; and

forming at least one gate structure on the active patterns.