METAL INSULATOR METAL CAPACITOR AND METHOD OF MANUFACTURING THE SAME

• US 20090001514A1
• Filed: 06/19/2008
• Published: 01/01/2009
• Est. Priority Date: 06/26/2007
• Status: Abandoned Application

• Current Assignee: Dongbu HiTek Co., Ltd.
• Original Assignee: Dongbu HiTek Co., Ltd.
• Inventors: Bae, Hyun-Su
• Application Number:
  US12/142,074
• Publication Number:
  US 20090001514A1
• Time in Patent Office: Days
• US Class Current: 257/532
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 28/40 Capacitors

Abstract

A metal-insulator-metal (MIM) capacitor may include a lower metal layer including a lower metal layer including a first lower metal layer and a second lower metal layer formed on a semiconductor substrate, an upper metal layer including a first upper metal layer and a second upper metal layer formed on the lower metal layer, a capacitor dielectric layer formed between the lower metal layer and the upper metal layer, a first bonding metal layer formed on the upper metal layer and a second bonding metal layer formed on the lower metal layer, a first connection wiring formed between the upper metal layer and the first bonding metal layer for directly connect the upper metal layer to the first bonding metal layer, and a second connection wiring formed between the lower metal layer and the second bonding metal layer for directly connecting the lower metal layer to the second bonding metal layer.

Claims

1. An apparatus comprising:

a lower metal layer including a first lower metal layer and a second lower metal layer formed on a semiconductor substrate;

an upper metal layer including a first upper metal layer and a second upper metal layer formed on the lower metal layer;

a capacitor dielectric layer formed between the lower metal layer and the upper metal layer;

a first bonding metal layer formed on the upper metal layer and a second bonding metal layer formed on the lower metal layer;

a first connection wiring formed between the upper metal layer and the first bonding metal layer for directly connect the upper metal layer to the first bonding metal layer; and

a second connection wiring formed between the lower metal layer and the second bonding metal layer for directly connecting the lower metal layer to the second bonding metal layer.

2. The apparatus of claim 1, wherein the capacitor dielectric layer comprises SiN.

3. The apparatus of claim 1, wherein the capacitor dielectric layer has a thickness in a range between 410 Å

to 510 Å

.

4. A method comprising:

forming a lower metal layer including a first lower metal layer and a second lower metal layer on a semiconductor substrate; and

then

forming a capacitor dielectric layer on the lower metal layer; and

then

forming an upper metal layer first upper metal layer and a second upper metal layer on a portion of the capacitor dielectric layer; and

then

forming a first silicon layer to cover the lower metal layer and the upper metal layer; and

then

forming a second silicon layer on the semiconductor substrate including the first silicon layer to level the semiconductor substrate; and

then

forming a first wiring pattern by etching the first and second silicon layers and the capacitor dielectric layer to expose a portion of the lower metal layer; and

then

forming a second wiring pattern by etching the first and second silicon layers to expose a portion of the upper metal layer; and

then

forming a third silicon layer on the second silicon layer; and

then

forming third and fourth wiring patterns by etching the third silicon layer in regions corresponding to the lower metal layer and the upper metal layer; and

then

simultaneously burying a metal material in the first and second wiring patterns to form connection wirings and a metal material in the third and fourth wiring patterns to form bonding metal layers.

5. The method of claim 4, further comprising, after forming the third silicon layer, forming a tetraethly orthosilicate (TEOS) layer on the third silicon layer.

6. The method of claim 5, wherein forming the third and fourth wiring patterns comprises etching the third silicon layer and the TEOS layer in regions corresponding to the lower metal layer and the upper metal layer.

7. The method of claim 4, wherein the first lower metal layer comprises Ti and the second lower metal layer comprises TiN.

8. The method of claim 7, wherein the first lower metal layer has a thickness in a range between 1,200 Å

to 1,400 Å and

the second lower metal layer has a thickness in a range between 400 Å

to 600 Å

.

9. The method of claim 4, wherein the capacitor dielectric layer comprises SiN and has a thickness in a range between 410 Å

to 510 Å

.

10. The method of claim 4, wherein the first upper metal layer comprises Ti and the second upper metal layer comprises TiN.

11. The method of claim 10, wherein the first upper metal layer has a thickness in a range between 1,200 Å

to 1,400 Å and

the second upper metal layer has a thickness in a range between 400 Å

to 600 Å

.

12. The method of claim 4, wherein the first silicon layer comprises at least one of SiH₄ and SiN and has a thickness in a range between 400 Å

to 600 Å

.

13. The method of claim 4, wherein the third silicon layer comprises SiN.

14. The method of claim 4, wherein the connection wirings and the bonding metal layers each comprise copper.

18. The method of claim 4, wherein the fifth metal layer and the sixth metal layer comprise Cu.

19. The method of claim 4, further comprising, after forming the fourth silicon layer, forming a tetraethly orthosilicate (TEOS) layer on the fourth silicon layer.

15. A method comprising:

sequentially forming a first metal layer on a semiconductor substrate and a second metal layer on the first metal layer; and

then

forming a first silicon layer on the second metal layer; and

then

sequentially forming a third metal layer on the capacitor dielectric layer and a fourth metal layer on the third metal layer; and

then

forming a second silicon layer on the semiconductor substrate including the first metal layer, the second metal layer, the first silicon layer, the third metal layer and the fourth metal layers; and

then

forming a third silicon layer having a planarized surface on the semiconductor substrate including the second silicon layer; and

then

performing a first etching process exposing the second metal layer and the fourth metal layer; and

then

forming a fourth silicon layer on the second silicon layer and the exposed second metal layer and the exposed fourth metal layer; and

then

performing a second etching process exposing the second metal layer, the fourth metal layer and the third silicon layer; and

then

simultaneously forming a first connection wiring connected to the fourth metal layer, a fifth metal layer connected to the first connection wiring, a second connection wiring connected to the second metal layer and sixth metal layer connected to the second connection wiring.

16. The method of claim 15, wherein the first metal layer and the third metal layer comprise Ti and the second metal layer and the fourth metal layer comprise titanium nitride.

17. The method of claim 15, wherein the first silicon layer comprises SiN, the second silicon layer comprises at least one of SiO₂ and SiN, the third silicon layer comprises at least one of SiH₄ and FSi, and the fourth silicon film comprises SiN.

20. The method of claim 15, wherein the first silicon layer has a thickness in a range between 410 Å

to 510 Å

.