Chip Attack Protection

• US 20090001821A1
• Filed: 12/11/2006
• Published: 01/01/2009
• Est. Priority Date: 01/24/2006
• Status: Active Grant

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: NDS Limited (Cisco Systems, Inc.)
• Inventors: Walker, John, Mantin, Itsik
• Granted Patent: US 7,966,666 B2
• Time in Patent Office: Days
• US Class Current: 307/413
• CPC Class Codes: G06F 21/87 by means of encapsulation, e.g. for integrated circuits
• CPC Class Codes: G06K 19/073 Special arrangements for circuits, e.g. for protecting identification code in memory protection against unauthorised use of computer memory G06F12/14
• CPC Class Codes: G09C 1/00 Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system cryptographic typewriters G09C3/00
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/29187 Ceramics, e.g. crystalline carbides, nitrides or oxides glass ceramics H01L2224/29188
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/48464 the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
• CPC Class Codes: H01L 2224/73257 Bump and wire connectors
• CPC Class Codes: H01L 2224/80 Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 2224/80896 between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06537 : Electromagnetic shielding
• CPC Class Codes: H01L 2225/06558 : the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
• CPC Class Codes: H01L 23/5225 : Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 23/5227 : Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/576 : using active circuits
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0102 : Calcium [Ca]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/10155 : being other than a cuboid
• CPC Class Codes: H01L 2924/10158 : at the passive surface
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01Q 1/2208 : associated with components used in interrogation type services, i.e. in systems for information exchange between an interrogator/reader and a tag/transponder, e.g. in Radio Frequency Identification [RFID] systems methods or arrangements for sensing record carriers, e.g. for reading patterns G06K7/00; record carrier for use with machines and with at least a part designed to carry digital markings G06K19/00
• CPC Class Codes: H01Q 1/526 : Electromagnetic shields
• CPC Class Codes: H04L 2209/12 : Details relating to cryptographic hardware or logic circuitry

Abstract

A system for protecting a chip with an integrated circuit disposed on a first surface, the system including, disposed on the first surface, a first antenna, signal analyzer, chip controller and a signal generator which is operative to supply an outbound signal for transmission by the first antenna, a circuit arrangement, disposed on a second surface of the chip, including a shielding arrangement and a second antenna to receive the outbound signal, the circuit arrangement being operative to transmit a return signal from the second antenna to the first antenna, such that a breach in the shielding arrangement results in a change in, or cessation of, the return signal for detection by the signal analyzer, and a chip controller disposed on the first surface being operative to perform an action on the integrated circuit in response to the detection of the breach. Related apparatus and methods also included.

Claims

1. A chip security system for protecting a chip from backside attack, the chip having a first surface and a second surface opposite the first surface, the first surface including an integrated circuit disposed thereon, the system comprising:

a first antenna disposed on the first surface;

a signal generator disposed on the first surface, the signal generator being operationally connected to the first antenna, the signal generator being operative to supply an outbound signal for transmission by the first antenna;

a circuit arrangement disposed on the second surface, the circuit arrangement including;

a second antenna to wirelessly receive the outbound signal transmitted by the first antenna thereby providing power to the circuit arrangement; and

a shielding arrangement to at least partially shield the second surface;

wherein the circuit arrangement is operative to transmit a return signal wirelessly from the second antenna to the first antenna, such that a breach in the shielding arrangement results in a change in, or cessation of, the return signal;

a signal analyzer disposed on the first surface, the signal analyzer being operationally connected to the first antenna, the signal analyzer being operative to detect the breach in the shielding arrangement from the change in, or the cessation, of the return signal; and

a chip controller disposed on the first surface, the chip control being operationally connected to the signal analyzer, the chip controller being operative to perform an action on the integrated circuit in response to the detection of the breach by the signal analyzer.

2. The system according to claim 1, wherein the antenna is comprised in the shielding arrangement.

3. The system according to claim 1, wherein the action of the chip controller includes resetting at least part of the integrated circuit.

4. The system according to claims 1, wherein the outbound signal includes a radio-frequency signal.

5. The system according to claim 1, wherein the circuit arrangement includes active circuit components, the circuit arrangement including:

a rectifier to rectify the outbound signal received by the second antenna;

a checker operationally connected to the rectifier, the checker being operative to check the integrity of the shielding arrangement; and

a reporter operationally connected to the checker and the second antenna, the reporter being operative to report back using the return signal to the signal analyzer via the second antenna and first antenna on the integrity of the shielding arrangement.

6. The system according to claim 5, wherein the return signal is a pulsed signal.

7. The system according to claim 5, wherein the return signal is a continuous signal.

8. The system according to claim 7, wherein the reporter is operative to form the return signal by amplitude modulating the outbound signal.

9. The system according to claim 1, wherein the circuit arrangement includes passive circuit components and excludes active circuit components.

10. The system according to claim 1, wherein the circuit arrangement includes a resonant circuit which has an associated resonant frequency.

11. The system according to claim 10, wherein the return signal has a Q-factor.

12. The system according to claim 10, wherein the outbound signal includes a swept frequency signal such that the return signal is a maximum when the swept frequency signal is at the resonant frequency.

13. The system according to claim 10, wherein the outbound signal includes a range of frequencies at the same time.

14. The system according to claim 13, wherein the signal generator forms the range of frequencies by generating white noise.

15. The system according to claim 11, wherein the signal analyzer is operative to analyze a change in at least one of the resonant frequency and the Q-factor of the return signal in order to detect the breach in the shielding arrangement.

16. The system according to claim 10, wherein the resonant circuit includes an inductor, a capacitor and a resistor, the second antenna being comprised in the inductor.

17. The system according to claim 16, wherein the capacitor is comprised in shielding arrangement.

18. The system according to claim 1, wherein the circuit arrangement is formed on a film which is mechanically connected to the second surface.

19. The system according to claim 18, wherein the film is a plastic film.

20. A chip security system, comprising two chips, each of the chips comprising:

a first surface and a second surface opposite the first surface;

an integrated circuit disposed on the first surface;

a shield disposed on the first surface; and

a shield manager disposed on the first surface, the shield manager being operative to check integrity of the shield and to perform an action on the integrated circuit in response to detecting a breach in the shield, wherein the chips are mechanically connected together via the second surface of each of the chips.

21. The system according to claim 20, wherein the chips are mechanically connected together by direct bonding.

22. The system according to claim 21, wherein the chips are bonded together by argon beam surface activation bonding.

23-31. -31. (canceled)

32. A chip security system, comprising:

a chip arrangement having a first surface and a second surface;

a plurality of shields including a first shield and a second shield, the first shield being disposed on the first surface, the second shield being disposed on the second surface;

an integrated circuit disposed on one of the first surface and the second surface; and

a shield manager disposed on a same surface of the chip arrangement as the integrated circuit, the shield manager being operationally connected to the shields and the integrated circuit, the shield manager including a number generator to generate a number, the shield manager being operative to send the number to the first shield, the first shield being operative to perform a first function on the number thereby yielding a first value if the first shield is intact, the second shield being operative to receive the first value and perform a second function on the first value yielding a second value if the second shield is intact, the shield manager including a check module to;

receive the second value; and

check a validity of the second value based on the number generated by the number generator in order to determine an integrity of the shields.

33. The system according to claim 32, wherein the check module is operative to:

perform a calculation using the first function and the second function with the number as input for the calculation; and

compare a result of the calculation to the second value in order to determine the integrity of the shields.

34-37. -37. (canceled)

38. A chip security system, comprising:

a chip arrangement having a first surface and a second surface;

a plurality of shields including a first shield and a second shield, the first shield being disposed on the first surface, the second shield being disposed on the second surface;

an integrated circuit disposed on the first surface; and

a shield manager disposed on the first surface, the shield manager being operationally connected to the shields and the integrated circuit, the shield manager including a number generator to generate a number, the shield manager being operative to send test data based on the number to the second shield, the second shield being operative to perform a function yielding a value if the second shield is intact, the shield manager including a check module to;

receive the value; and

perform an operation on the value in order to determine an integrity of the second shield.

39. The system according to claim 38, wherein the test data is equal to the number and wherein the check module is operative to:

perform a calculation using the function with the number as input for the calculation; and

compare a result of the calculation to the value in order to determine the integrity of the second shield.

40-44. -44. (canceled)

45. An integrated circuit protection system, comprising:

a silicon substrate having a surface;

an integrated circuit disposed on the surface of the silicon substrate, the integrated circuit including;

a first layer including a plurality of structures, the structures including at least one bilayer structure, the at least one bilayer structure including a polycrystalline silicon sub-layer and a metal silicide sub-layer; and

a second layer including a plurality of metal elements, the first layer being closer to the surface that the second layer; and

a shield arrangement including a polycrystalline silicon sub-layer and a metal silicide sub-layer, the shield arrangement being disposed in the first layer such that the shield arrangement does not perform an electronic function in the integrated circuit.

46. The system according to claim 45, wherein the shield arrangement is disposed in the first layer such that a view seen by an infrared microscope of at least one of the metal elements is at least partially obscured when the infrared microscope images the integrated circuit through the silicon substrate.

52. The system according to claim 45, wherein the first layer defines a plane, the shield arrangement being disposed in the first layer such that the shield arrangement and at least one of the structures form a region, the region including at least one gap, the gap having a minimum dimension measured parallel to the plane of less than about 550 nanometers.

47-51. -51. (canceled)

53-55. -55. (canceled)

56. An integrated circuit protection system, comprising:

a silicon substrate having a surface; and

an integrated circuit disposed on the surface of the silicon substrate, the integrated circuit including;

a first layer including a plurality of structures including a at least one bilayer structure having a polycrystalline silicon sub-layer and a metal silicide sub-layer; and

a second layer including a plurality of metal elements, the first layer being closer to the surface that the second layer;

a shield arrangement including a polycrystalline silicon sub-layer and a metal silicide sub-layer, the shield arrangement being disposed in the first layer; and

a breach-detection circuit operatively connected to the shield arrangement such that a breach in the shield arrangement is detected by the breach-detection circuit, the breach-detection circuit being operative to perform an action on another part of the integrated circuit in response to the detection of the breach.

57-59. -59. (canceled)