Accurate Capacitance Measurement for Ultra Large Scale Integrated Circuits
First Claim
1. A method of measuring parasitic capacitance in a semiconductor device, said method comprising:
- providing a first test structure having a first array of unit cells, each unit cell of said first array comprising a first gate electrode, a first plurality of to-be-measured contacts, and a first plurality of adjacent conductive features;
applying a first bias to the first gate electrode and a second bias to the first plurality of to-be-measured contacts and to the first plurality of adjacent conductive features;
measuring a first capacitance on said first test structure between said first bias and said second bias;
providing a second test structure formed having a second array of unit cells, wherein each unit cell of said second array comprises a second gate electrode and a second plurality of adjacent conductive features, said each unit cell of said second array having no to-be-measured contacts;
wherein the second gate electrode is substantially similar to the first gate electrode, and the second plurality of adjacent conductive features is substantially similar to the first plurality of adjacent conductive features;
applying the first bias to the second gate electrode and the second bias to the second plurality of adjacent conductive features;
measuring a second capacitance on the second test structure between the first bias and the second bias; and
calculating a parasitic capacitance Cco-po between said first gate electrode and said first plurality of to-be-measured contacts using said first and second capacitances.
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Accused Products
Abstract
Test structures and methods for measuring contact and via parasitic capacitance in an integrated circuit are provided. The accuracy of contact and via capacitance measurements are improved by eliminating not-to-be-measured capacitance from the measurement results. The capacitance is measured on a target test structure that has to-be-measured contact or via capacitance. Measurements are then repeated on a substantially similar reference test structure that is free of to-be-measured contact or via capacitances. By using the capacitance measurements of the two test structures, the to-be-measured contact and via capacitance can be calculated.
108 Citations
20 Claims
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1. A method of measuring parasitic capacitance in a semiconductor device, said method comprising:
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providing a first test structure having a first array of unit cells, each unit cell of said first array comprising a first gate electrode, a first plurality of to-be-measured contacts, and a first plurality of adjacent conductive features; applying a first bias to the first gate electrode and a second bias to the first plurality of to-be-measured contacts and to the first plurality of adjacent conductive features; measuring a first capacitance on said first test structure between said first bias and said second bias; providing a second test structure formed having a second array of unit cells, wherein each unit cell of said second array comprises a second gate electrode and a second plurality of adjacent conductive features, said each unit cell of said second array having no to-be-measured contacts;
wherein the second gate electrode is substantially similar to the first gate electrode, and the second plurality of adjacent conductive features is substantially similar to the first plurality of adjacent conductive features;applying the first bias to the second gate electrode and the second bias to the second plurality of adjacent conductive features; measuring a second capacitance on the second test structure between the first bias and the second bias; and calculating a parasitic capacitance Cco-po between said first gate electrode and said first plurality of to-be-measured contacts using said first and second capacitances. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of measuring parasitic capacitance in a semiconductor, said method comprising:
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providing a first test structure comprising a first conductive comb structure and a second conductive comb structure complementary to the first comb, each of said first and second conductive comb structures being formed in a first interconnect layer, and a third conductive comb structure and a fourth conductive comb structure complementary to the third comb, each said third and fourth conductive comb structures being formed in a second interconnect layer; wherein the first conductive comb structure couples with the fourth conductive comb structure through a first plurality of to-be-measured via formed at the cross-over regions of the first and the fourth conductive comb structures, and the second conductive comb structure couples with the third conductive comb structure through a second plurality of to-be-measured via formed at the cross-over regions of the second and the third conductive comb structures; applying a first bias to the first and the fourth conductive comb structures, and a second bias to the second and the third conductive comb structures; measuring a first capacitance on said first test structure between said first bias and said second bias; providing a second test structure comprising a fifth conductive comb structure and a sixth conductive comb structure complementary to the fifth conductive comb structure, both being formed in the first interconnect layer, and a seventh conductive comb structure and an eighth conductive comb structure complementary to the seventh conductive comb structure, both being formed in the second interconnect layer; wherein the fifth and the eight conductive comb structures are substantially similar to the first and the fourth conductive comb structures, respectively, being free of to-be-measured vias formed between the fifth and the eight conductive comb structures; wherein the sixth and the seventh conductive comb structures are substantially similar to the second and the third conductive comb structures, respectively, being free of to-be-measured vias formed between the sixth and the seventh conductive comb structures; applying the first bias to the fifth and the eight conductive comb structures, and the second bias to the sixth and the seventh conductive comb structures; measuring a second capacitance on the second test structure between the first bias and the second bias; and calculating a parasitic capacitance Cv of to-be-measured via using said first and said second capacitances. - View Dependent Claims (9, 10, 11, 12, 13)
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14. A test structure formed on an semiconductor substrate for measuring the parasitic capacitance between a via and adjacent conductive features of a semiconductor device, said test structure comprising:
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a first conductive comb structure and a second conductive comb structure complementary to the first comb structure, each of said first and said second conductive comb structures being formed in a first interconnect layer; a third conductive comb structure and a fourth conductive comb structure complementary to the third comb structure, each of said third and said fourth conductive comb structures being formed in a second interconnect layer; a first plurality of to-be-measured via formed at the cross-over regions of said first conductive comb structure and said fourth conductive comb structure, electrically coupling said first conductive comb structure with said fourth conductive comb structure; and a second plurality of to-be-measured via formed at the cross-over regions of said second conductive comb structure and said third conductive comb structure, electrically coupling said second conductive comb structure with said third conductive comb structure. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification