CONFIGURABLE IC WITH DESKEWING CIRCUITS

• US 20090002022A1
• Filed: 06/27/2007
• Published: 01/01/2009
• Est. Priority Date: 06/27/2007
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Hutchings, Brad
• Granted Patent: US 7,839,162 B2
• Time in Patent Office: Days
• US Class Current: 326/38
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17764 for reliability

Abstract

Some embodiments provide a configurable integrated circuit (IC) comprising multiple deskew circuits for delaying data passage. Each of the deskew circuits comprises a stepwise delay circuit with multiple outputs and an input selection circuit with multiple inputs. Multiple outputs connect to multiple inputs.

In some embodiments the configurable IC is a subcycle reconfigurable IC. In some such embodiments each of the deskew circuits further includes a space-time load control circuit for commanding the stepwise delay circuit to load during a selected subcycle. In some embodiments the multiple deskew circuits send data to trigger circuit. In some such embodiments the trigger circuit triggers a trace buffer to stop recording a data stream. In some such embodiments the trigger circuit triggers the trace buffer to stop after a programmable delay.

Claims

1. A configurable integrated circuit (IC) comprising:

a) a plurality of deskew circuits for delaying data passage, each of said deskew circuits comprising;

i) a stepwise delay circuit with a plurality of outputs; and

ii) an input selection circuit with a plurality of inputs, wherein at least a plurality of said outputs connect to at least a plurality of said inputs.

2. The configurable IC of claim 1, wherein said configurable IC is a subcycle reconfigurable IC.

3. The configurable IC of claim 2, wherein each of said deskew circuits further comprises a space-time load control circuit for commanding the stepwise delay circuit to load during a selected subcycle.

4. The configurable IC of claim 1, wherein said plurality of deskew circuits sends data to a trigger circuit.

5. The configurable IC of claim 4, wherein said trigger circuit triggers a trace buffer to stop recording a data stream.

6. The reconfigurable IC of claim 5, wherein said trigger circuit triggers said trace buffer to stop after a programmable delay.

7. The reconfigurable IC of claim 6, wherein said trace buffer is for recording for N subcycles, wherein N is a number.

8. The reconfigurable IC of claim 7, wherein said programmable delay is about half of N subcycles.

9. The reconfigurable IC of claim 5, wherein said trace buffer is a circular trace buffer.

10. The configurable IC of claim 1, wherein said plurality of deskew circuits temporally aligns a set of incoming bits.

11. The configurable IC of claim 10, wherein temporally aligning said set of incoming bits comprises compensating for a set of delays between a production of said set of incoming bits within said configurable IC and an arrival of individual bits of said set of incoming bits at said deskew circuits.

12. The configurable IC of claim 1, wherein said plurality of deskew circuits comprises at least 48 deskew circuits.

13. The configurable IC of claim 1 further comprising a second input selection circuit for selecting from a set of incoming data lines, said first input selection circuit comprising a first set of inputs and an output, wherein said output communicably connects to said stepwise delay circuit.

14. The configurable IC of claim 13 further comprising a multi-layered transport network for transporting data to said plurality of multi-input deskew circuits.

15. The configurable IC of claim 14, wherein data lines from a first layer of said multi-layered transport network connect to at least a plurality of said multi-input deskew circuits.

16. The configurable IC of claim 15, wherein data lines from a second layer of said multi-layered transport network connect to at least a plurality of said multi-input deskew circuits.

17. The configurable IC of claim 16, wherein data lines from a first layer of said multi-layered transport network connect to all of said multi-input deskew circuits.

18. A reconfigurable IC comprising:

a) a plurality of deskew circuits comprising a set of outputs; and

b) a trigger circuit for triggering a trace buffer, wherein said set of outputs of said plurality of deskew circuits are communicably connected to a set of inputs of said trigger circuit.

19. The reconfigurable IC of claim 18, wherein said trigger circuit triggers a trace buffer to stop recording a data stream.

20. The reconfigurable IC of claim 19, wherein said trigger circuit triggers said trace buffer to stop after a programmable delay.

21. The reconfigurable IC of claim 20, wherein said trace buffer is a circular trace buffer.

22. The reconfigurable IC of claim 21, wherein:

a) said reconfigurable IC is a subcycle reconfigurable IC; and

b) said circular trace buffer is for recording for N subcycles, wherein N is a number.

23. The reconfigurable IC of claim 22, wherein said delay is about half of N subcycles.

24. For an integrated circuit with a trace buffer, and trigger circuits for triggering said trace buffer to stop recording, a method comprising:

a) temporally aligning a set of data bits into a temporally aligned set of data bits; and

b) passing said temporally aligned set of data bits to said trigger circuits.

25. The method of claim 24 further comprising recording said set of data bits at said trace buffer.

26. The method of claim 24, wherein said temporally aligning is by a set of deskew circuits.

27. The method of claim 24, wherein at least one of said set of deskew circuits is a multi-input deskew circuit.

28. A circuit comprising:

a) a plurality of multi-input deskew circuits; and

b) a multi-layer transport network, wherein a plurality of outputs of a set of at least two layers of said multi-input transport network connect to a plurality of inputs of said plurality of multi-input deskew circuits.

29. The circuit of claim 28, wherein substantially all outputs of a first layer of said set of at least two layers of said multi-layer transport network connect to inputs of each of said plurality of multi-input deskew circuits.

30. The circuit of claim 29, wherein a first subset of outputs of a second layer of said set of at least two layers connect to inputs of each of a first subset of said plurality of multi-input deskew circuits.

31. The circuit of claim 30, wherein a second subset of outputs of the second layer of said set of at least two layers connect to inputs of each of a second subset of said plurality of multi-input deskew circuits.

32. The circuit of claim 31, wherein said second subset of said plurality of multi-input deskew circuits comprises about half of said plurality of multi-input deskew circuits.

33. The circuit of claim 31, wherein a third subset of outputs of the second layer of said set of at least two layers connect to inputs of each of a third subset of said plurality of multi-input deskew circuits.

34. The circuit of claim 31, wherein said first subset of said plurality of multi-input deskew circuits comprises about one third of said plurality of multi-input deskew circuits.

35. The circuit of claim 34, wherein said second subset of said plurality of multi-input deskew circuits comprises about one third of said plurality of multi-input deskew circuits.

36. The circuit of claim 35, wherein said third subset of said plurality of multi-input deskew circuits comprises about one third of said plurality of multi-input deskew circuits.