TRANSPORT NETWORK FOR A CONFIGURABLE IC

• US 20090002024A1
• Filed: 06/27/2007
• Published: 01/01/2009
• Est. Priority Date: 06/27/2007
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Redgrave, Jason, Hutchings, Brad
• Granted Patent: US 7,501,855 B2
• Time in Patent Office: Days
• US Class Current: 326/41
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17764 for reliability

Abstract

Some embodiments provide a configurable integrated circuit (IC) with an arrangement of circuit elements, a trace buffer, a transport network separate from the arrangement of circuit elements. The transport network transports data from the arrangement of circuit elements to the trace buffer.

In some embodiments the configurable IC is on a single chip. In some embodiments the configurable IC further includes trigger circuits for triggering the trace buffer to stop recording a set of data. In some such embodiments the configurable IC further includes deskew circuits for temporally aligning a subset of the data. In some embodiments the subset of the data passes through the transport network on its way to the deskew circuits.

Claims

1. A configurable integrated circuit (IC) comprising:

a) an arrangement of circuit elements;

b) a trace buffer;

c) a transport network separate from said arrangement of circuit elements;

wherein said transport network is for transporting data from said arrangement of circuit elements to the trace buffer;

d) trigger circuits for triggering the trace buffer to stop recording a set of data; and

e) deskew circuits for temporally aligning a subset of said data.

4. The configurable IC of claim 1, wherein said deskew circuits are for sending temporally aligned data to said trigger circuits.

5. The configurable IC of claim 1, wherein said transport network is further for transporting said subset of said data on said data'"'"'s way to said deskew circuits.

6. The configurable IC of claim 1, wherein said trigger circuits are separate from said arrangement.

7. The configurable IC of claim 1, wherein a subset of said data passes through said transport network on its way to said trigger circuits.

9. The configurable IC of claim 1, wherein said arrangement comprises a plurality of columns and said transport network receives said data from the plurality of columns of said arrangement.

11. The configurable IC of claim 9, wherein said transport network is configurable to send selected bits of said data from each of several of said plurality of columns to said trace buffer.

12. The configurable IC of claim 9, wherein said transport network comprises at least 12 data lines.

13. The configurable IC of claim 9, wherein said transport network comprises at least 36 data lines.

14. The configurable IC of claim 9, wherein said transport network comprises at least 48 data lines.

15. The configurable IC of claim 1, wherein said transport network comprises a plurality of levels of partial crossbars.

16. The configurable IC of claim 1, wherein said transport network is connected to a plurality of data lines from a debug network.

17. The configurable IC of claim 1, wherein said transport network comprises a plurality of levels.

18. The configurable IC of claim 1, wherein the transport network is separated by being some distance away from said arrangement of circuit elements.

19. The configurable IC of claim 1, wherein the transport network is separated by being outside said arrangement of circuit elements, but is immediately adjacent to said arrangement of circuit elements.

20. The configurable IC of claim 1, wherein the IC is on a single chip.

2. (canceled)

3. (canceled)

8. A configurable integrated circuit (IC) comprising:

a) an arrangement of circuit elements;

b) a trace buffer;

c) a transport network separate from said arrangement of circuit elements;

wherein said transport network transports data from said arrangement of circuit elements to the trace buffer; and

d) trigger circuits for triggering the trace buffer to stop recording a set of data, wherein said trigger circuits comprise a programmable delay for triggering the buffer after a delay of a plurality of clock cycles.

10. A configurable integrated circuit (IC) comprising:

a) an arrangement of circuit elements;

b) a trace buffer;

c) a transport network separate from said arrangement of circuit elements;

wherein said transport network is for transporting data from said arrangement of circuit elements to the trace buffer, wherein said transport network receives said data from a plurality of columns of said arrangement; and

d) trigger circuits for triggering the trace buffer to stop recording a set of data, wherein said transport network is further for sending a subset of said data to said trigger circuits.

21. A reconfigurable integrated circuit (IC) comprising:

a) an arrangement of circuit elements;

b) a transport network separate from said arrangement of circuit elements;

wherein said transport network is for transporting data from said arrangement of circuit elements to a trace buffer on said reconfigurable IC

c) trigger circuits for triggering the trace buffer to stop recording a set of data; and

d) deskew circuits for temporally aligning a subset of said data.

22. The reconfigurable IC of claim 21, wherein the reconfigurable IC is a subcycle reconfigurable IC.

23. (canceled)