INTEGRATED CIRCUIT WITH DELAY SELECTING INPUT SELECTION CIRCUITRY

• US 20090002045A1
• Filed: 06/27/2007
• Published: 01/01/2009
• Est. Priority Date: 06/27/2007
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Redgrave, Jason, Hutchings, Brad
• Granted Patent: US 7,652,498 B2
• Time in Patent Office: Days
• US Class Current: 327/276
• CPC Class Codes: H03K 19/177 arranged in matrix form

Abstract

Some embodiments provide an integrated circuit (IC) with a delay select input selection circuit. The delay select input selection circuit comprises a first input selection circuit, a first storage element, a second storage element, and a first input line branching into multiple input lines. The multiple input lines include at least a second, third, and fourth input line. The second input line is communicably connected to a first input of the first input selection circuit. The third input line enters the first storage element. The fourth input line enters the second storage element. An output from the first storage element is communicably connected to a second input of the first input selection circuit. An output from the second storage element is communicably connected to a third input of the first input selection circuit.

Claims

1. An integrated circuit (IC) comprising a delay select input selection circuit, said delay select input selection circuit comprising:

a) a first input selection circuit;

b) a first storage element;

c) a second storage element; and

d) a first input line branching into a plurality of input lines comprising at least a second, third, and fourth input line, wherein;

i) said second input line is communicably connected to a first input of said first input selection circuit;

ii) said third input line enters said first storage element;

iii) said fourth input line enters said second storage element;

iv) an output from said first storage element is communicably connected to a second input of said first input selection circuit; and

v) an output from said second storage element is communicably connected to a third input of said first input selection circuit.

2. The IC of claim 1, wherein said first input selection circuit further comprises a third input communicably connected to a second input selection circuit of a second delay select input selection circuit.

3. The IC of claim 2, wherein an output of said first input selection circuit is communicably connected to an input of a third input selection circuit of a third delay select input selection circuit.

4. The IC of claim 1, wherein the IC is a configurable IC.

5. The IC of claim 1, wherein the IC is a reconfigurable IC.

6. The IC of claim 1, wherein the IC is a subcycle reconfigurable IC.

7. The IC of claim 1, wherein said first storage element comprises a latch.

8. An integrated circuit (IC) comprising a chain of delay select input selection circuits, each delay select input selection circuit of said chain of delay select input selection circuits comprising:

a) a first input selection circuit;

b) a first storage element; and

c) a first input line wherein the first input line branches into a plurality of input lines comprising at least a second input line and a third input line, wherein;

i) said second input line is communicably connected to a first input selection circuit input of said first input selection circuit;

ii) said third input line enters said first storage element; and

iii) an output from said first storage element is communicably connected to a second input selection circuit input of said first input selection circuit.

9. The IC of claim 8, wherein an output from each of a plurality of first input selection circuits of a plurality of said delay select input selection circuits of said chain of delay select input selection circuits communicably connects to a third input line of a next input selection circuit in a next delay select input selection circuit in said chain of delay select input selection circuits.

10. The IC of claim 9, wherein each of a plurality of said delay select input selection circuits comprises a second storage element, wherein:

a) a fifth input line enters said second storage element; and

b) an output from said second storage element is communicably connected to a fourth input of said input selection circuit.

11. The IC of claim 9 further comprising a plurality of chains of delay select input selection circuits.

12. The IC of claim 9 further comprising a plurality of additional data lines branching from said outputs.

13. The IC of claim 12, wherein subsets of said plurality of additional data lines connect to input selection circuits.

14. An integrated circuit (IC) comprising a transport network comprising a plurality of delay select input selection circuits.

15. The IC of claim 14, wherein the IC is a configurable IC.

16. The IC of claim 14, wherein the IC is a reconfigurable IC.

17. The IC of claim 14, wherein the IC is a subcycle reconfigurable IC.

18. A delay select input selection circuit comprising:

a) an input selection circuit; and

b) a first input line wherein the first input line branches into a plurality of input lines comprising at least a second input line and a third input line;

wherein;

i) said second input line is communicably connected to a first input of said input selection circuit;

ii) said third input line enters a delaying circuit; and

iii) an output from said delaying circuit is communicably connected to a second input of said input selection circuit wherein the input selection circuit comprises at least one input not communicatively connected to a branch of said first input line.

19. The delay select input selection circuit of claim 18, wherein the delaying circuit is a latch.

20. An configurable integrated circuit (IC) comprising:

a) a debug network comprising;

i) an output network with a fixed capacity; and

ii) a storage element for storing at least one of a first bit and a second bit, wherein said first and second bits are read concurrently, but cannot be outputted concurrently along the output network.

21. The configurable IC of claim 20, wherein said first and second bits cannot be outputted concurrently along the output network because of output congestion at certain locations of said output network.

22. The configurable IC of claim 21, wherein said congestion is because at least one of the certain locations is in the output path of at least one of the first bit and the second bit.

23. The configurable IC of claim 21, wherein said congestion is because at least one of the certain locations is in the output path of bits other than said first bit and said second bit.

24. The configurable IC of claim 20, wherein the first bit is outputted later than the second bit.

25. A configurable integrated circuit (IC) comprising:

a) a debug network with a fixed output capacity; and

b) a storage element for storing one of a first bit and a second bit that are received concurrently by the debug network but that cannot be output concurrently because of said fixed output capacity.

26. The IC of claim 25, wherein said second bit is outputted by said debug network after said first bit.

27. The IC of claim 26, wherein said debug network comprises a transport network and wherein said storage element is part of said transport network.