Computer theft deterrence technology
First Claim
Patent Images
1. A system, comprising:
- a security timer;
a communication logic to communicate with a theft deterrence service provider (TDSP) to request a signal to update the security timer; and
a theft deterrence logic to disable a computer associated with the system, the theft deterrence logic to disable the computer upon the expiration of the security timer,at least one of the security timer, the communication logic, and the theft deterrence logic being part of an integrated embedded controller (IEC), the IEC being a member of a chipset of the computer.
0 Assignments
0 Petitions
Accused Products
Abstract
A system embodiment associated with making a computer a less desirable target for a thief is described. A system embodiment may include a security timer that is to be periodically refreshed. If the security timer is not periodically refreshed, then a computer in which the system embodiment is located may be disabled by a theft deterrence logic. The system embodiment may also include a communication logic to communicate with a TDSP to request a signal to update the security timer. While a system embodiment is described, it is to be appreciated that other system embodiments having different elements and that method embodiments may be described.
-
Citations
15 Claims
-
1. A system, comprising:
-
a security timer; a communication logic to communicate with a theft deterrence service provider (TDSP) to request a signal to update the security timer; and a theft deterrence logic to disable a computer associated with the system, the theft deterrence logic to disable the computer upon the expiration of the security timer, at least one of the security timer, the communication logic, and the theft deterrence logic being part of an integrated embedded controller (IEC), the IEC being a member of a chipset of the computer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
-
-
12. A method, comprising:
-
examining a security timer of an IEC implemented at the microcode level in a chipset of a computer; requesting from an external security provider a signal to update the security timer; and disabling the computer upon determining that the security timer has expired. - View Dependent Claims (13, 14, 15)
-
Specification