Biasing scheme for large format CMOS active pixel sensors

• US 20090002536A1
• Filed: 07/03/2008
• Published: 01/01/2009
• Est. Priority Date: 04/09/2003
• Status: Active Grant

• Current Assignee: Isao Takayanagi, Junichi Nakamura
• Original Assignee: Isao Takayanagi, Junichi Nakamura
• Inventors: Takayanagi, Isao, Nakamura, Junichi
• Granted Patent: US 8,988,568 B2
• Time in Patent Office: Days
• US Class Current: 348/308
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
• CPC Class Codes: H04N 25/671 for non-uniformity detection or correction
• CPC Class Codes: H04N 25/677 for reducing the column or line fixed pattern noise
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
• CPC Class Codes: H04N 3/1568 for disturbance correction or prevention within the image-sensor, e.g. biasing, blooming, smearing correction circuits H04N25/62

Abstract

An image sensor includes circuitry compensating for voltage drops in a V_SS line. The image sensor includes a plurality of photoreceptors arranged in a pixel array having a number of column lines, and read-out circuitry on the column lines. The read-out circuitry provides substantially equal currents on each column line so as to compensate for voltage drops in the V_SS line and provide more accurate pixel signals. The image sensor also includes circuitry for filtering noise from a voltage supply line, and for providing hard and/or soft reset operations.

Claims

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8. An image sensor comprising:

a pixel array including a plurality of column lines;

a plurality of load transistors, each connected respectively to one of the column lines; and

a circuit applying a substantially equal gate-source voltage to each of the load transistors.

9. A sensor as in claim 8, wherein the circuit comprises a level shift circuit.

10. A sensor as in claim 8, wherein the circuit comprises a clamp circuit.

11. An image sensor comprising:

a pixel array including a plurality of column lines; and

differential amplifier circuitry connected to each of the column lines for maintaining a substantially equal current on each of the plurality of column lines.

12. An image sensor as in claim 11, wherein the differential amplifier circuitry includes a differential amplifier, and a pair of reference voltage inputs to the differential amplifier.

13. An image sensor as in claim 12, further comprising power inputs to the differential amplifier.

14. An image sensor as in claim 13, wherein one of the power inputs is V_AA and the other is V_SS.

15. An image sensor as in claim 14, wherein power input V_AA is different from a V_AA—

_PIX input to the pixel array.

16. An active pixel sensor (APS) comprising:

a plurality of photoreceptors arranged in an array to form a plurality of columns of image sensors, each column of image sensors having circuitry that compensates for voltage drops in at least one of a voltage supply line and a ground line connecting the plurality of columns of image sensors, wherein each of said plurality of columns of image sensors has readout circuitry that compensates for voltage drops in a V_SS line and the readout circuitry includes a load transistor on each column of image sensors, and a level shift circuit supplying a constant gate-source voltage to the load transistor.

23. An APS as in claim 16, wherein the level shift circuit is connected between the V_SS line and the gate of the load transistor.

24. An APS as in claim 16, wherein the readout circuitry includes a clamp circuit supplying a constant gate-source voltage to the load transistor.

25. An APS as in claim 24, wherein the clamp circuit includes a clamp capacitor charged to a clamping voltage during a period when row select pulses are turned off.

26. An APS as in claim 16, wherein the readout circuitry includes a differential amplifier connected between each column of image sensors and the V_SS line.

27. An APS as in claim 26, wherein an output of the differential amplifier connected to the column line.

28. An APS as in claim 16, wherein each column of image sensors as reset circuitry that compensates for voltage drops in a voltage supply line.

29. An APS as in claim 28, wherein the reset circuitry includes a hard reset switch provided in a voltage line to the pixel for hard resetting.

30. An APS as in claim 29, wherein the hard reset switch comprises an n-MOS transistor operating in a saturation region.

31. An APS as in claim 29, further comprising a soft reset switch provided in parallel to the hard reset switch.

32. An APS as in claim 31, wherein the soft reset switch comprises a p-MOS transistor.

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35. A method of operating an image sensor such that pixel signals are compensated for voltage drops in a V_SS line comprising:

charging a clamping capacitor supplying voltage to a gate of a load transistor connected between each column of an image sensor array and the V_SS line;

selecting a row to obtain a charge signal from a selected row of photoreceptors; and

sampling a signal on each column of the selected row.

41. The method of claim 35, wherein the act of charging a clamping capacitor is performed during a vertical blanking period for said array.

42. The method of claim 35, wherein the act of selecting a row to obtain a charge signal from a selected row of photoreceptors comprises applying a row select pulse to a row select transistor, and wherein the act of charging a clamping capacitor is performed at a time when said row select pulse is not being applied.

36. A method of operating an image sensor comprising:

supplying a constant current to a gate of a load transistor connected between each column of an image sensor array and ground;

selecting a row to obtain a charge signal from a selected row of photoreceptors; and

sampling a signal on each column of the selected row.

43. The method of claim 36, wherein the act of supplying a constant current to a gate of a load transistor is performed by a level shift circuit.

44. The method of claim 36, wherein each load transistor has a respective, associated level shift circuit for each column line in the image sensor.

45. The method of claim 44, wherein an input of the level shift circuit for column i is V_SS—

_coli and an output is V<sub>SScol—

i</sub>+Δ

V, wherein Δ

V is a pre-determined voltage.

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