Predictive DMA data transfer
First Claim
1. An image processing device comprising:
- a marking engine;
an image compressor configured to compress image data;
an image decompressor configured to decompress image data previously compressed by the image compressor;
an electronic memory organized as storage blocks each having a storage block size;
a direct memory access (DMA) engine configured to transfer compressed image data from the image compressor into the electronic memory and to transfer compressed image data from the electronic memory to the image decompressor;
a central processing unit (CPU) configured to coordinate operations of at least the marking engine and DMA engine to cause the marking engine to generate markings in accordance with selected image data input to the image compressor; and
a transfer block size estimator configured to adjust a transfer block size used in transfer of compressed image data from the image compressor into the electronic memory based on analysis of previous transfers of compressed image data from the image compressor into the electronic memory, the DMA engine being further configured to transfer a unit of compressed image data having the transfer block size from the image compressor into the electronic memory without intervention of the CPU.
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Accused Products
Abstract
A compression and storage device comprises: a compressor configured to compress data; a central processing unit (CPU) configured to control storage of the compressed data and to perform at least one additional task; an electronic memory organized as storage blocks each having a storage block size; a direct memory access (DMA) engine configured to operate autonomously from the CPU to transfer a current transfer block of compressed data into one or more storage blocks of the electronic memory; and a transfer block size estimator configured to select a transfer block size for the current transfer block based on previous DMA transfers of compressed data, the selected transfer block size being generally different from the storage block size.
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Citations
27 Claims
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1. An image processing device comprising:
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a marking engine; an image compressor configured to compress image data; an image decompressor configured to decompress image data previously compressed by the image compressor; an electronic memory organized as storage blocks each having a storage block size; a direct memory access (DMA) engine configured to transfer compressed image data from the image compressor into the electronic memory and to transfer compressed image data from the electronic memory to the image decompressor; a central processing unit (CPU) configured to coordinate operations of at least the marking engine and DMA engine to cause the marking engine to generate markings in accordance with selected image data input to the image compressor; and a transfer block size estimator configured to adjust a transfer block size used in transfer of compressed image data from the image compressor into the electronic memory based on analysis of previous transfers of compressed image data from the image compressor into the electronic memory, the DMA engine being further configured to transfer a unit of compressed image data having the transfer block size from the image compressor into the electronic memory without intervention of the CPU. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A compression and storage device comprising:
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a compressor configured to compress data; a central processing unit (CPU) configured to control storage of the compressed data and to perform at least one additional task; an electronic memory organized as storage blocks each having a storage block size; a direct memory access (DMA) engine configured to operate autonomously from the CPU to transfer a current transfer block of compressed data into one or more storage blocks of the electronic memory; and a transfer block size estimator configured to select a transfer block size for the current transfer block based on previous DMA transfers of compressed data, the selected transfer block size being generally different from the storage block size. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. An image processing device comprising:
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a marking engine; an image compressor configured to compress image data; an image decompressor configured to decompress image data previously compressed by the image compressor; an electronic memory; a direct memory access (DMA) engine configured to transfer compressed image data from the image compressor into the electronic memory and to transfer compressed image data from the electronic memory to the image decompressor; a central processing unit (CPU) configured to coordinate operations of at least the marking engine and DMA engine to cause the marking engine to generate markings in accordance with selected image data input to the image compressor; and a transfer block size estimator configured to adjust a transfer block size for autonomous transfer of compressed image data from the image compressor into the electronic memory based on analysis of previous transfers of compressed image data from the image compressor into the electronic memory. - View Dependent Claims (23, 24)
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25. A compression and storage method comprising:
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compressing data; storing compressed data during compression to an electronic memory organized as storage blocks each having a storage block size, the storing being performed by a direct memory access (DMA) engine configured to operate autonomously from a CPU to transfer a current transfer block of compressed data into one or more storage blocks of the electronic memory; and selecting a transfer block size for the current transfer block based on previous DMA transfers of compressed data, the selected transfer block size being generally different from the storage block size. - View Dependent Claims (26, 27)
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Specification