Method of Forming a Substrate Core Structure Using Microvia Laser Drilling and Conductive Layer Pre-Patterning And Substrate Core Structure Formed According to the Method

• US 20090002958A1
• Filed: 06/28/2007
• Published: 01/01/2009
• Est. Priority Date: 06/28/2007
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Gurumurthy, Charan, Li, Yonggang, Salama, Islam, Azimi, Hamid
• Granted Patent: US 8,440,916 B2
• Time in Patent Office: Days
• US Class Current: 361/748
• CPC Class Codes: H05K 1/0298 Multilayer circuits
• CPC Class Codes: H05K 1/0306 Inorganic insulating substrates, e.g. ceramic, glass
• CPC Class Codes: H05K 1/115 Via connections; Lands around holes or via connections H05K1/112 takes precedence
• CPC Class Codes: H05K 1/18 Printed circuits structurally associated with non-printed electric components H05K1/0201, H05K1/023, H05K1/0243, and H05K1/16 take precedence
• CPC Class Codes: H05K 2201/0394 Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
• CPC Class Codes: H05K 2201/09563 Metal filled via
• CPC Class Codes: H05K 2201/0959 Plated through-holes or plated blind vias filled with insulating material
• CPC Class Codes: H05K 2201/0969 Apertured conductors
• CPC Class Codes: H05K 3/0032 of organic insulating material
• CPC Class Codes: H05K 3/0035 of blind holes, i.e. having a metal layer at the bottom
• CPC Class Codes: H05K 3/0038 combined with laser drilling through a metal layer
• CPC Class Codes: H05K 3/426 initial plating of through-holes in substrates without metal
• CPC Class Codes: H05K 3/427 initial plating of through-holes in metal-clad substrates
• CPC Class Codes: H05K 3/429 Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
• CPC Class Codes: H05K 3/4644 by building the multilayer layer by layer, i.e. build-up multilayer circuits making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602
• CPC Class Codes: H05K 3/4652 Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern H05K3/4647 takes precedence
• CPC Class Codes: Y10T 29/49126 Assembling bases
• CPC Class Codes: Y10T 29/49155 Manufacturing circuit on or in base
• CPC Class Codes: Y10T 29/49165 by forming conductive walled aperture in base

Abstract

A method of fabricating a substrate core structure comprises, providing first and second patterned conductive layers defining openings therein on each side of a starting insulating layer; providing a first and a second supplemental insulating layers onto respective ones of a first and a second patterned conductive layer; laser drilling a set of via openings extending through at least some of the conductive layer openings of the first and second patterned conductive layers; filling the set of via openings with a conductive material to provide a set of conductive vias; and providing a first and a second supplemental patterned conductive layer onto respective ones of the first and the second supplemental insulating layers, the set of conductive vias contacting the first supplemental patterned conductive layer at one side thereof and the second supplemental patterned conductive layer at another side thereof.

Claims

1. A method of fabricating a substrate core structure comprising:

providing a starting insulating layer;

providing a first patterned conductive layer on one side of the starting insulating layer, and a second patterned conductive layer on another side of the starting insulating layer each of the first patterned conductive layer and the second patterned conductive layer defining conductive layer openings therein;

providing a supplemental insulating layer onto the first patterned conductive layer, and a second supplemental insulating layer onto the second patterned conductive layer;

laser drilling a set of via openings extending from a side of the second supplemental insulating layer farthest from the second patterned conductive layer to a side of the first supplemental insulating layer farthest from the first patterned conductive layer such that the via openings extend through at least some of the conductive layer openings of the first patterned conductive layer and the second patterned conductive layer;

filling the set of via openings with a conductive material to provide a set of conductive vias;

providing a first supplemental patterned conductive layer onto the first supplemental insulating layer and a second supplemental patterned conductive layer onto the second supplemental insulating layer, the set of conductive vias contacting the first supplemental patterned conductive layer at one side thereof, and the second supplemental patterned conductive layer at another side thereof.

2. The method of claim 1, wherein filling the set of via openings includes plating.

3. The method of claim 2, wherein filling the set of via openings further includes plugging after plating such that the set of conductive vias includes plated plugged conductive vias.

4. The method of claim 1, wherein the starting insulating layer and the supplemental insulating layer each comprise at least one of a glass epoxy resin and bismaleimide-triazine (BT).

5. The method of claim 1, wherein providing the first patterned conductive layer and the second patterned conductive layer includes:

providing, respectively, a first initial conductive layer on one side of the starting insulating layer and a second initial conductive layer on an opposite side of the starting insulating layer to yield a core layer; and

patterning respective ones of the first initial conductive layer and the second initial conductive layer to yield the first and second patterned conductive layers.

6. The method of claim 1, wherein providing the first supplemental insulating layer and the second supplemental insulating layer includes laminating.

7. The method of claim 1, wherein providing the first supplemental patterned conductive layer includes,

providing a first supplemental conductive layer on one side of the first supplemental insulating layer prior to providing the first supplemental insulating layer onto the first patterned conductive layer such that after providing the first supplemental insulating layer onto the first patterned conductive layer, the first supplemental insulating layer is disposed between the first patterned conductive layer and the first supplemental conductive layer, the set of via openings extending to the first supplemental conductive layer.

8. The method of claim 7, wherein:

providing the first supplemental patterned conductive layer includes patterning the first supplemental conductive layer to yield the first supplemental patterned conductive layer; and

providing the second supplemental patterned conductive layer includes;

providing an second supplemental conductive layer on one side of the second supplemental insulating layer after filling the set of via openings, and

patterning the second supplemental conductive layer to yield the second supplemental patterned conductive layer.

9. The method of claim 7, wherein providing the second supplemental patterned conductive layer includes providing an second supplemental conductive layer on one side of the second supplemental insulating layer prior to providing the second supplemental insulating layer onto the second patterned conductive layer, such that, after providing the second supplemental insulating layer onto the second patterned conductive layer, the second supplemental insulating layer is disposed between the second patterned conductive layer and the second supplemental conductive layer, the set of via openings extending through the second supplemental conductive layer to the first supplemental conductive layer.

10. The method of claim 9, wherein the first supplemental conductive layer and the second supplemental conductive layer have a thickness below about 2 microns.

11. The method of claim 9, wherein:

providing the first supplemental patterned conductive layer includes;

plating a first extra conductive layer onto the first supplemental conductive layer; and

patterning a combination of the first supplemental conductive layer and the first extra conductive layer to yield the first supplemental patterned conductive layer; and

providing the second supplemental patterned conductive layer includes,

plating a second extra conductive layer onto the second supplemental conductive layer; and

patterning a combination of the second supplemental conductive layer and the second extra conductive layer to yield the second supplemental patterned conductive layer.

12. The method of claim 3, wherein:

plating includes providing plating layers to cover walls of the set of via openings and exposed surfaces of respective ones of the first supplemental insulating layer and second supplemental insulating layer, and

providing the first supplemental patterned conductive layer and the second supplemental patterned conductive layer includes using semi-additive patterning onto plating layers disposed on respective ones of the first supplemental insulating layer and the second supplemental insulating layer.

13. The method of claim 5, wherein the core layer is a double-sided copper clad core.

29. The method of claim 1, wherein filling the set of via openings includes plating.

30. The method of claim 2, wherein filling the set of via openings further includes plugging after plating such that the set of conductive vias includes plated plugged conductive vias.

14. A multilayer substrate core structure including:

a starting insulating layer;

a first patterned conductive layer on one side of the starting insulating layer, and a second patterned conductive layer on another side of the starting insulating layer;

a first supplemental insulating layer on the first patterned conductive layer;

a second supplemental insulating layer on the second patterned conductive layer;

a first supplemental patterned conductive layer on the first supplemental insulating layer;

a second supplemental patterned conductive layer on the second supplemental insulating layer;

a set of conductive vias provided in corresponding laser-drilled via openings extending from the second supplemental patterned conductive layer to the first supplemental patterned conductive layer, the via openings further extending through the first patterned conductive layer and the second patterned conductive layer.

15. The substrate core structure of claim 14, wherein the set of conductive vias include a plated conductive material therein.

16. The substrate core structure of claim 14, wherein the set of conductive vias include a plugging material therein.

17. The substrate core structure of claim 14, wherein the set of conductive vias includes a skip via.

18. The substrate core structure of claim 14, wherein the set of conductive vias includes a padless via.

19. The substrate core structure of claim 14 wherein the starting insulating layer and the supplemental insulating layer each comprise at least one of a glass epoxy resin and bismaleimide-triazine (BT).

20. A system comprising:

an electronic assembly including;

a multilayer substrate core structure including;

a starting insulating layer;

a first patterned conductive layer on one side of the starting insulating layer, and a second patterned conductive layer on another side of the starting insulating layer;

a first supplemental insulating layer on the first patterned conductive layer;

a second supplemental insulating layer on the second patterned conductive layer;

a first supplemental patterned conductive layer on the first supplemental insulating layer;

a second supplemental patterned conductive layer on the second supplemental insulating layer;

a set of conductive vias provided in corresponding laser-drilled via openings extending from the second supplemental patterned conductive layer to the first supplemental patterned conductive layer, the via openings further extending through the first patterned conductive layer and the second patterned conductive layer; and

a main memory coupled to the electronic assembly.

21. The system of claim 20, wherein the set of conductive vias include an plated conductive material there n.

22. The system of claim 20, wherein the set of conductive vias include a plugging material therein.

23. The system of claim 20, wherein the set of conductive vias includes a skip via.

24. The system of claim 20, wherein the set of conductive vias includes a padless via extending through the starting insulating layer.

25. The system of claim 20, wherein the starting insulating layer and the supplemental insulating layer each comprise at least one of a glass epoxy resin and bismaleimide-triazine (BT).

26. A method of fabricating a substrate core structure comprising:

providing a starting insulating layer;

providing a patterned conductive layer on one side of the starting insulating layer, the first patterned conductive layer defining conductive layer openings therein;

providing a supplemental insulating layer onto the first patterned conductive layer,

laser drilling a set of via openings extending from a side of the supplemental insulating layer farthest from the patterned conductive layer to a side of the starting insulating layer farthest from the patterned conductive layer such that the via openings extend through at least some of the conductive layer openings of the patterned conductive layer;

filling the set of via openings with a conductive material to provide a set of conductive vias,

27. The method of claim 26, wherein the set of via openings includes a padless via.

28. The method of claim 26, wherein the set of via openings includes a skip via.