Method of making 3D R/W cell with reduced reverse leakage

• US 20090003036A1
• Filed: 06/29/2007
• Published: 01/01/2009
• Est. Priority Date: 06/29/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Petti, Christopher J., Kumar, Tanmay
• Granted Patent: US 7,800,939 B2
• Time in Patent Office: Days
• US Class Current: 365/148
• CPC Class Codes: G11C 13/00 Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/009 Write using potential difference applied between cell electrodes
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: H01L 27/101 including resistors or capacitors only
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H10B 63/00 Resistance change memory devices, e.g. resistive RAM [ReRAM] devices

Abstract

A method of making a nonvolatile memory device includes forming a semiconductor diode steering element, and forming a semiconductor read/write switching element.

Claims

1. A method of making a nonvolatile memory device, comprising:

forming a semiconductor diode steering element; and

forming a semiconductor read/write switching element.

2. The method of claim 1, further comprising forming at least one conductive layer located between the steering element and the read/write switching element.

3. The method of claim 2, wherein the at least one conductive layer comprises a titanium nitride layer.

4. The method of claim 2, wherein the steering element, the at least one conductive layer and the read/write switching element are arranged in series and together comprise a nonvolatile memory cell.

5. The method of claim 4, further comprising forming a first electrode and a second electrode such that they electrically contact the nonvolatile memory cell.

6. The method of claim 5, wherein the read/write switching element comprises a resistor.

7. The method of claim 6, wherein:

the read/write switching element comprises amorphous, polycrystalline or a combination amorphous and polycrystalline Group IV semiconductor resistor;

the steering element comprises a crystallized polycrystalline Group IV semiconductor diode; and

the at least one conductive layer contacts the steering element and the read/write switching element.

8. The method of claim 7, further comprising crystallizing the steering element located in contact with a silicide crystallization template layer, while the read/write switching element does not contact a silicide crystallization template, such that after the step of crystallizing, the steering element has a lower resistivity than the read/write switching element.

9. The method of claim 8, further comprising patterning the read/write switching element, the at least one conductive layer and the steering element into a vertical pillar, wherein the vertical pillar is located between the first electrode and the second electrode.

10. The method of claim 5, wherein in use, the read/write switching element of the memory cell switches from a first resistivity state to a second resistivity state different from the first resistivity state in response to an applied electrical pulse.

11. The method of claim 10, wherein steering element does not switch from the first resistivity state to the second resistivity state in response to the applied electrical pulse.

12. The method of claim 11, wherein an application of a second electrical pulse is adapted to switch the read/write switching element from the second resistivity state to the first resistivity state.

13. A method of making a nonvolatile memory device, comprising:

forming a semiconductor diode steering element;

forming a semiconductor resistor read/write switching element;

forming at least one conductive layer located between the steering element and the read/write switching element;

forming a first electrode electrically contacting the steering element; and

forming a second electrode electrically contacting the read/write switching element;

wherein the read/write switching element, the at least one conductive layer and the steering element are arranged in series in a pillar between the first electrode and the second electrode.

14. The method of claim 13, wherein:

the read/write switching element comprises amorphous, polycrystalline or a combination amorphous and polycrystalline Group IV semiconductor resistor and the steering element comprises a crystallized polycrystalline Group IV semiconductor diode;

the at least one conductive layer contacts the steering element and the read/write switching element; and

a silicide crystallization template layer contacts the steering element.

15. The method of claim 14, wherein the method comprises:

forming the first electrode over a substrate;

forming the semiconductor diode steering element on the first electrode;

forming a titanium or cobalt first conductive layer on the diode steering element;

forming a titanium nitride second conductive layer on the titanium or cobalt layer;

forming the resistor read/write switching element;

patterning the diode steering element, the first and the second conductive layers and the resistor read/write switching element into a pillar;

annealing the device to form a titanium or cobalt silicide layer by reacting the first conductive layer with the diode steering element;

crystallizing the diode steering element in contact with the titanium or cobalt silicide layer, such that the diode steering element has a lower resistivity than the resistor read/write switching element; and

forming the second electrode on the resistor read/write switching element.

16. A method of operating a nonvolatile memory device, comprising:

providing a non-volatile memory cell comprising a semiconductor diode steering element, a semiconductor read/write switching element, and at least one conductive layer located between the steering element and the read/write switching element;

first switching the read/write switching element from a first resistivity state to a second resistivity state different from the first resistivity state; and

second switching the read/write switching element from the second resistivity state to the first resistivity state.

17. The method of claim 16, wherein the first and the second steps of switching comprise applying a first and a second electrical pulse, respectively, to the steering element and to the read/write switching element.

18. The method of claim 17, wherein steering element does not switch from the first resistivity state to the second resistivity state in response to the first and the second applied electrical pulses.

19. The method of claim 18, wherein:

the steering element is formed in a low resistivity state which does not change in response to the first and the second applied electrical pulses;

the read/write switching element is formed in a high resistivity state which changes in response to the first and the second applied electrical pulses; and

the first and the second electrical pulses comprise forward bias electrical pulses of a different magnitude from each other.

20. The method of claim 16, wherein the read/write switching element comprises a resistor.