FLASH MEMORY DEVICE AND METHOD FOR ADJUSTING READ VOLTAGE OF FLASH MEMORY DEVICE

• US 20090003058A1
• Filed: 06/26/2008
• Published: 01/01/2009
• Est. Priority Date: 06/28/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kang, Dong-Ku
• Granted Patent: US 8,040,725 B2
• Time in Patent Office: Days
• US Class Current: 365/185.30
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells

Abstract

A flash memory device includes a cell array and a read voltage adjuster. The cell array includes a first field having first memory cells and a second field having second memory cells. The read voltage adjuster determines a read voltage for reading first data from the first memory cells of the first field with reference to second data read from the memory cells of the second field.

Claims

1. A flash memory device, comprising:

a cell array comprising a first field having a first plurality of memory cells and a second field having a second plurality of memory cells; and

a read voltage adjuster for determining a read voltage for reading first data from the first plurality of memory cells of the first field with reference to second data read from the second plurality of memory cells of the second field.

2. The flash memory device as set forth in claim 1, wherein the first plurality of memory cells and the second plurality of memory cells are connected to the same word line.

3. The flash memory device as set forth in claim 2, wherein the second plurality of memory cells of the second field are programmed in a highest state.

4. The flash memory device as set forth in claim 3, wherein the second plurality of memory cells of the second field are sensed by an index read voltage.

5. The flash memory device as set forth in claim 4, wherein the index read voltage is a verifying voltage for programming the second plurality of memory cells of the second field into the highest state.

6. The flash memory device as set forth in claim 5, wherein the read voltage adjuster counts a number of bits corresponding to on-cells from the second data.

7. The flash memory device as set forth in claim 6, wherein the read voltage adjuster adjusts the read voltage lower based on the number of bits corresponding to the on-cells.

8. The flash memory device as set forth in claim 1, wherein the first and second pluralities of memory cells are multi-level cells, each multi-level cell storing multi-bit data.

9. The flash memory device as set forth in claim 8, wherein the cell array further comprises a plurality of flag cells for indicating the number of bits stored in the first and second pluralities of memory cells.

10. The flash memory device as set forth in claim 9, wherein the first plurality of memory cells, the second plurality of memory cells and the plurality of flag cells are connected to the same word line.

11. The flash memory device as set forth in claim 10, wherein the second field comprises a plurality of index fields corresponding to pages of the multi-bit data.

12. The flash memory device as set forth in claim 11, wherein the second data are read out from the second plurality of memory cells belonging to one of the plurality of index fields in accordance with page information read by at least one flag cell.

13. The flash memory device as set forth in claim 12, wherein each of the index fields comprises memory cells, which are sensed by index read voltages having different levels.

14. The flash memory device as set forth in claim 1, further comprising:

a high voltage generator configured to generate the read voltage.

15. A flash memory device, comprising:

a plurality of memory cells, each of which is included in one of a main field, a spare field, and an index field;

a page buffer connected to bit lines of the plurality memory cells;

a high voltage generator for providing a read voltage for a word line of the plurality of memory cells; and

a read voltage adjuster for determining the read voltage for reading first data from the memory cells of the main field with reference to second data read from the memory cells of the index field and the spare field, and for setting the high voltage generator to generate the read voltage.

16. The flash memory device as set forth in claim 15, wherein the plurality memory cells are connected to the same word line.

17. The flash memory device as set forth in claim 16, wherein the memory cells of the spare field comprise flag cells for storing page information indicating the number of pages programmed in the main field.

18. The flash memory device as set forth in claim 17, wherein the index field comprises a plurality of cell fields, each corresponding to the number of pages.

19. The flash memory device as set forth in claim 18, wherein the plurality of cell fields include memory cells of the plurality of memory cells, the memory cells of the plurality cell fields being sensed by index read voltages having different levels, respectively.

20. The flash memory device as set forth in claim 19, wherein the second data includes the page information and index data read from the memory cells of the plurality of cell fields corresponding to the page information.

21. The flash memory device as set forth in claim 20, wherein the read voltage adjuster counts a number of bits corresponding to on-cells from the index data.

22. The flash memory device as set forth in claim 21, wherein the read voltage adjuster determines the read voltage in accordance with the counted number of bits.

23. The flash memory device as set forth in claim 22, wherein the read voltage adjuster adjusts the read voltage to be lower based on the number of bits.

24. The flash memory device as set forth in claim 15, further comprising:

a command register and control logic block for activating the read voltage adjuster in response to a read command.

25. A reading method of a multi-bit flash memory device, the method comprising:

reading index data from memory cells belonging to an index field in response to a read command; and

adjusting a read voltage with reference to the index data.