MEMORY TEST MODE FOR CHARGE RETENTION TESTING

• US 20090003099A1
• Filed: 06/28/2007
• Published: 01/01/2009
• Est. Priority Date: 06/28/2007
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: SAFVI, Anwar, JAZAYERI, Reza
• Granted Patent: US 7,545,698 B2
• Time in Patent Office: Days
• US Class Current: 365/201
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/50016 of retention

Abstract

One embodiment includes a dynamic memory operable in different refresh modes including an autonomous refresh mode in which the refresh rate is set by an internal self refresh timer circuit on the memory circuit die, and a test refresh mode in which the refresh rate is set by a timer circuit external to the memory circuit die. Other embodiments are described and claimed.

Claims

1. A method, comprising:

disabling an autonomous refresh mode of a dynamic random access memory circuit on a die which is adapted to autonomously refresh the memory cells of the memory circuit at a first autonomous refresh mode rate;

enabling a test refresh mode;

refreshing said memory cells during said test refresh mode at a second test refresh mode rate which is higher than said first autonomous refresh mode rate and is a function of the output of a timer circuit external to the die of the memory circuit; and

testing said memory circuit wherein the results of said testing is a function of the charge retention of said memory cells.

2. The method of claim 1 wherein said second rate is 5-50% faster than said first rate.

3. The method of claim 1 wherein said autonomous refresh mode disabling and said test refresh mode enabling includes setting contents of a control register on said die.

4. The method of claim 1 further comprising:

disabling said test refresh mode;

enabling said autonomous refresh mode; and

refreshing said memory cells during said autonomous refresh mode at said first autonomous refresh mode rate which is lower than said second test refresh mode rate and is a function of the output of a self timer circuit on the die of the memory circuit.

5. The method of claim 4 wherein said autonomous mode refreshing includes generating refresh signals by a refresh signal generation circuit in response to refresh trigger signals output by a self timer circuit on said die during said autonomous mode refreshing, and wherein said first autonomous refresh rate is determined by the rate at which refresh trigger signals are output by said self timer circuit on said die.

6. The method of claim 5 wherein said test mode refreshing includes generating refresh signals by said refresh signal generation circuit in response to refresh trigger signals output by said external timer circuit during said test mode refreshing, and wherein said second test refresh rate is determined by the rate of at which refresh trigger signals are output by said external timer circuit.

7. The method of claim 6 wherein said autonomous refresh mode disabling includes disconnecting a refresh trigger signal output of said self timer circuit from a refresh trigger signal input of said refresh signal generation circuit and said test mode enabling includes connecting an external port to said refresh trigger signal input of said refresh signal generation circuit, wherein said port is adapted to receive refresh trigger signals output by said external timer circuit.

8. The method of claim 7 wherein said autonomous mode disabling and said test mode enabling includes setting a content of a control register on said die, and said disconnecting and connecting are in response to said control register content.

9. A device for use with an external timer circuit, comprising:

a first die; and

an integrated circuit comprising a dynamic random access memory circuit disposed on said die and having a plurality of memory cells;

said integrated circuit further including a refresh signal generation circuit disposed on said die and adapted to refresh said memory cells in response to trigger signals, a self timer circuit adapted to provide a plurality of refresh trigger signals at a first rate;

a port disposed on said die and adapted to receive a plurality of refresh trigger signals from said external timer circuit; and

a timer selection circuit disposed on said die and adapted to, in response to a test mode enable signal, disconnect said self timer circuit from said refresh generation circuit during a test refresh mode, and to couple refresh trigger signals from said port to said refresh generation circuit, wherein said refresh signal generation circuit is adapted to refresh said memory cells at a second test mode rate in response to refresh trigger signals provided by said timer circuit external to said die during said test refresh mode.

10. The device of claim 9 wherein said timer selection circuit is adapted to, in response to an autonomous refresh mode enable signal, disconnect said port from said refresh signal generation circuit during an autonomous refresh mode, and to couple refresh trigger signals from said self timer circuit to said refresh signal generation circuit, wherein said refresh signal generation circuit is adapted to refresh said memory cells autonomously at said first refresh rate in response to refresh trigger signals provided by said self timer circuit during said autonomous refresh mode.

11. The device of claim 10 wherein said second test mode rate is 5-50% faster than said first autonomous refresh mode rate.

12. The device of claim 9 wherein integrated circuit on said die further includes a control register disposed on said die and adapted to store a refresh mode enable signal, and wherein said timer selection circuit is adapted to, in response to the contents of said control register to selectively couple refresh trigger signals from said self timer circuit to said refresh generation circuit during said first autonomous mode, to disconnect said self timer circuit from said refresh generation circuit during said test mode, and couple said port to said refresh generation circuit, during said test mode, wherein said second test mode rate is determined by said timer circuit external to said die.

13. The device of claim 9 further comprising a second die and a package within which said first and second dies are disposed, said second die having at least one integrated circuit which includes a central processing unit, said memory circuit of said first die being coupled to said central processing unit, and wherein said device is a computer system further comprising:

a video controller coupled to said central processing unit;

storage coupled to said central processing unit;

an input device coupled to said central processing unit; and

an output device coupled to said central processing unit.

14. The device of claim 9 further comprising a second die and a package within which said first and second dies are disposed, said second die having at least one integrated circuit which includes a flash memory.