METHOD FOR FABRICATING AN INTER DIELECTRIC LAYER IN SEMICONDUCTOR DEVICE

• US 20090004849A1
• Filed: 11/27/2007
• Published: 01/01/2009
• Est. Priority Date: 06/28/2007
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Eun, Byung Soo
• Granted Patent: US 8,592,326 B2
• Time in Patent Office: Days
• US Class Current: 438/654
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/76837 Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
• CPC Class Codes: H10B 12/482 Bit lines

Abstract

In a method for fabricating an inter dielectric layer in semiconductor device, a primary liner HDP oxide layer is formed by supplying a high density plasma (HDP) deposition source to a bit line stack formed on a semiconductor substrate. A high density plasma (HDP) deposition source is supplied to the bit line stack to form a primary liner HDP oxide layer. The primary liner HDP oxide layer is etched to a predetermined depth to form a secondary liner HDP oxide layer. An interlayer dielectric layer is formed to fill the areas defined by the bit line stack where the secondary liner HDP oxide layer is located.

Claims

1. A method for fabricating an inter dielectric layer in a semiconductor device, comprising:

forming a bit line stack over a semiconductor substrate;

supplying a high density plasma (HDP) deposition source to the bit line stack to form a primary liner HDP oxide layer on the bit line stack;

etching the primary liner HDP oxide layer to a predetermined thickness to form a secondary liner HDP oxide layer; and

forming an interlayer dielectric layer to fill areas defined by the bit line stack where the secondary liner HDP oxide layer is formed.

2. The method of claim 1, further comprising preheating the bit line stack before forming the primary liner HDP oxide layer.

3. The method of claim 2, wherein the preheating of the bit line stack comprises:

loading the semiconductor substrate into an HDP chamber; and

applying a predetermined power to the HDP chamber while supplying oxygen (O₂) gas, argon (Ar) gas, and helium (He) gas into the HDP chamber.

4. The method of claim 1, wherein the HDP deposition source comprises a source gas comprising silane (SiH₄) gas and oxygen (O₂) gas, and an additive gas comprising helium (He) gas.

5. The method of claim 1, wherein the formation of the primary liner HDP oxide layer comprises maintaining a bottom bias of an HDP chamber at less than 500 W.

6. The method of claim 1, comprising forming the primary liner HDP oxide layer to a thickness ranging from about 500 Å

to about 600 Å

.

7. The method of claim 1, comprising forming the secondary liner HDP oxide layer using a fluorine-based etch gas.

8. The method of claim 1, wherein the secondary liner HDP oxide layer is formed by etching the primary liner HDP oxide layer by a etching thickness ranging from about 150 Å

to about 190 Å

.

9. The method of claim 1, wherein the forming of the interlayer dielectric layer comprises:

coating a flowable layer comprising a solvent on the semiconductor substrate where the secondary liner HDP oxide layer is formed;

evaporating the solvent by heating the flowable layer at a temperature between about 130°

C. to about 150°

C.; and

curing the flowable layer to form an oxide layer.

10. The method of claim 9, wherein the flowable layer comprises a spinon dielectric (SOD) layer comprising polysilizane (PSZ).

11. The method of claim 9, comprising curing for about 1 hour while supplying IL of hydrogen (H₂) gas and 2 L of oxygen (O₂) gas at a temperature between about 450°

C. and about 550°

C.

12. A method for fabricating an inter dielectric layer in a semiconductor device, comprising:

forming a bit line stack on a semiconductor substrate;

forming a spacer-shaped liner on the bit line stack to expose the top of the bit line stack and the semiconductor substrate having a lower structure using a high density plasma (HDP) oxide layer; and

coating a flowable layer filling areas defined by the spacer-shaped liner on the semiconductor substrate; and

curing the flowable layer to form a dense interlayer dielectric layer.

13. The method of claim 12, wherein the forming of the spacer-shaped liner comprises:

forming a primary liner oxide layer using an HDP oxide on the semiconductor substrate where the bit line stack is formed; and

etching the primary liner oxide layer to form the spacer-shaped liner exposing the bit line stack and the semiconductor substrate.

14. The method of claim 12, wherein the flowable layer comprises a spin-on dielectric (SOD) layer comprising polysilizane (PSZ).

15. The method of claim 13, wherein the forming of the dense interlayer dielectric layer comprises:

evaporating a solvent contained in the flowable layer by heating the flowable layer at a temperature between about 130°

C. and about 150°

C.; and

curing the flowable layer for about 1 hour while supplying 1 L of hydrogen (H₂) gas and 2 L of oxygen (O₂) gas at a temperature between about 450°

C. and about 550°

C.