SEMICONDUCTOR MEMORY DEVICE

• US 20090006687A1
• Filed: 06/25/2008
• Published: 01/01/2009
• Est. Priority Date: 06/27/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Shibata, Tomoyuki
• Granted Patent: US 7,941,573 B2
• Time in Patent Office: Days
• US Class Current: 710/106
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/107 Serial-parallel conversion of data or prefetch
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Data transfer bus charging/discharging current is reduced in a semiconductor memory device. In a data transfer device that sequentially transfers bit sequences in parallel through a plurality of buses from a transmit unit 10 to a receive unit 20, the transmit circuit 10 includes a flag generation circuit 11 and an encoding circuit 12. The flag generation circuit 11 generates a flag indicating whether bit inversion has occurred in consecutive bits in each of the bit sequences to be transferred through the buses and transmits the generated flag to the receive unit 20. The encoding circuit 12 encodes the bit sequences based on the flag, for transmission to the receive unit 20. The receive unit includes a decoding circuit 21 that decodes the bit sequences based on the bit sequences and the flag.

Claims

1. A data transfer device that sequentially transfers bit sequences in parallel from a transmit unit to a receive unit through a plurality of buses, wherein

said transmit unit comprises:

a flag generation circuit which generates a flag indicating whether or not bit inversion has occurred in consecutive bits in each of the bit sequences to be transferred through said buses, and transmits the generated flag to said receive unit; and

an encoding circuit that encodes the bit sequences based on the flag, for transmission to said receive unit; and

said receive unit comprises;

a decoding circuit that decodes the bit sequences based on the bit sequences and the flag.

2. The data transfer device according to claim 1, wherein the data transfer device is a data transfer device which sequentially transfers the bit sequences in parallel from said transmit unit to said receive unit through two buses, based on a 4:

2 parallel-to-serial conversion.

3. The data transfer device according to claim 2, wherein said flag generation circuit is so configured as to generate a valid flag, only when the bit inversion has occurred in the consecutive bits of the bit sequences to be transferred through said two buses, respectively, and to transmit the valid flag to said receive unit;

said encoding circuit is so configured as to invert the bit sequences only when the flag is valid and to transmit the inverted bit sequences to said receive unit; and

said decoding circuit is so configured as to invert the bit sequences only when the flag is valid.

4. The data transfer device according to claim 3, wherein

said flag generation circuit is so configured as to generate a valid flag:

in case where a flag generated by said flag generation circuit followed by transmission to said receive unit is received, or a flag generated by said flag generation circuit is stored, and consecutive bits to be transferred through said two buses, respectively, are both inverted and the flag is not valid;

or

in case where the bit inversion does not occur in at least one of the consecutive bits to be transferred through said two buses, respectively, and the flag is valid; and

to transmit the generated valid flag to said receive unit.

6. The data transfer device according to claim 1, wherein

said encoding circuit comprises:

an XOR circuit that receives the first bit or the third bit and the inversion flag, for output to said first bus; and

an XOR circuit that receives the second bit or the fourth bit and the inversion flag, for output to said second bus.

7. The data transfer device according to claim 1, wherein

said decoding circuit comprises:

an XOR circuit that receives the first bit or the third bit and the inversion flag; and

an XOR circuit that receives the second bit or the fourth bit and the inversion flag.

8. The data transfer device according to claim 1, wherein

said flag generation circuit comprises:

a first XOR circuit that receives the first bit and the third bit;

a second XOR circuit that receives the second bit and the fourth bit;

an AND circuit that receives outputs of said first and second XOR circuits; and

a third XOR circuit that receives an output of said AND circuit and the inversion flag, for output to said third bus.

9. A multi-stage data transfer device comprising:

the data transfer device according to claim 1, as first, second, and third data transfer devices;

said multi-stage data transfer device being so configured to supply outputs of said first and second data transfer devices to said third data transfer device.

10. A semiconductor memory device comprising:

the data transfer device according to claim 1.

5. A data transfer device configured to repeat a step of transmitting a first bit through a first bus, a second bit through a second bus, a third bit through said first bus, and a fourth bit through said second bus, from a transmit unit to a receive unit, wherein said data transfer device further comprises:

a third bus configured to transfer an inversion flag;

said transmit unit further comprises;

a flag generation circuit; and

an encoding circuit;

said receive unit further comprises;

a decoding circuit;

said flag generation circuit receives the first through fourth bits and the inversion flag, and is so configured as to output to said third bus the inversion flag as a valid flag (i) when bit inversion between the first and third bits and bit inversion between the second and fourth bits occur and the inversion flag is not valid, and (ii) when at least one of the bit inversion between the first and third bits and the bit inversion between the second and fourth bits does not occur and the inversion flag is valid; and

otherwise to output to said third bus the inversion flag as an invalid flag;

said encoding circuit receives the first through fourth bits and the inversion flag, and is so configured as to invert the first through fourth bits when the inversion flag is valid, and otherwise to output the first through fourth bits to said first and second bus without alteration; and

said decoding circuit receives the first through fourth bits and the inversion flag, and is so configured as to invert the first through fourth bits when the inversion flag is valid, and otherwise to output the first through fourth bits without alteration.

11. A data transfer method of sequentially transferring bit sequences in parallel from a transmit unit to a receive unit through a plurality of buses, wherein

said method comprises:

generating a flag indicating whether bit inversion has occurred in consecutive bits in each of the bit sequences to be transferred through said buses, and transmitting the generated flag to said receive unit;

encoding the bit sequences based on the flag, for transmission to said receive unit; and

decoding the bit sequences based on the bit sequences and the flag.

12. The data transfer method according to claim 11, wherein the data transfer method is a data transfer method of sequentially transferring the bit sequences in parallel from said transmit unit to said receive unit through two buses, based on a 4:

2 parallel-to-serial conversion.

13. The data transfer method according to claim 12, wherein

in said generating, the flag being valid is generated only when the bit inversion has occurred in the consecutive bits of said each of the bit sequences to be transferred through said different buses, respectively, and the valid flag is transmitted to said receive unit;

in said encoding, the bit sequences are inverted only when the flag is valid and the inverted bit sequences are transmitted to said receive unit; and

in said decoding, the bit sequences are inverted only when the flag is valid.

14. The data transfer method according to claim 13, wherein

in said flag generating, a valid flag is generated and transmitted to said receive unit only:

in case where the flag generated in said flag generating followed by transmission to said receive unit is received or a flag generated in said flag generating is stored, and consecutive bits to be transferred through said two buses, respectively, are both inverted and the flag is not valid;

or

in case where the bit inversion does not occur in at least one of the consecutive bits to be transferred through said two buses, respectively, and the flag is valid receive unit.