SYSTEM AND METHOD FOR PROGRAMMABLE BANK SELECTION FOR BANKED MEMORY SUBSYSTEMS

• US 20090006718A1
• Filed: 06/26/2007
• Published: 01/01/2009
• Est. Priority Date: 06/26/2007
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Hoenicke, Dirk, Chen, Dong, Gara, Alan G., Ohmacht, Martin, Giampapa, Mark E., Blumrich, Matthias A., Salapura, Valentina, Sugavanam, Krishnan
• Granted Patent: US 7,793,038 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0851 Cache with interleaved addressing
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A programmable memory system and method for enabling one or more processor devices access to shared memory in a computing environment, the shared memory including one or more memory storage structures having addressable locations for storing data. The system comprises: one or more first logic devices associated with a respective one or more processor devices, each first logic device for receiving physical memory address signals and programmable for generating a respective memory storage structure select signal upon receipt of pre-determined address bit values at selected physical memory address bit locations; and, a second logic device responsive to each the respective select signal for generating an address signal used for selecting a memory storage structure for processor access. The system thus enables each processor device of a computing environment memory storage access distributed across the one or more memory storage structures.

Claims

1. A programmable memory system for enabling one or more processor devices access to shared memory in a computing environment, said shared memory comprising one or more memory storage structures having addressable locations for storing data for said one or more processor devices, said system comprising:

one or more first logic devices associated with a respective said one or more processor devices, each one or more first logic devices for receiving physical memory address signals and programmable for generating a respective memory storage structure select signal upon receipt of pre-determined address bit values at selected physical memory address bit locations;

a second logic device responsive to each said respective select signal for generating an address signal used for selecting a memory storage structure for processor access,

wherein each processor device of said computing system is enabled memory storage access distributed across said one or more memory storage structures.

2. The programmable memory system as claimed in claim 1, further comprising means receiving unselected bit values of said received physical memory address signal for generating an offset bit vector signal used to enable processor device access to memory locations within a selected memory storage structure.

3. The programmable memory system as claimed in claim 2, wherein said selected address bit values are programmable for enabling a single processor exclusive access to a single memory storage structure.

4. The programmable memory system as claimed in claim 2, wherein each said associated first programmable logic device includes a multiplexer device programmed to respond to pre-determined bit values at pre-determined physical memory address bit locations.

5. The programmable memory system as claimed in claim 2, wherein each said associated first programmable logic device implements logic for applying a hash function to said physical memory address signals.

6. The programmable memory system as claimed in claim 5, wherein each said associated first programmable logic device comprises an XOR reduction tree for applying a hash function, an output of each said XOR reduction tree generating said memory storage structure select signal.

7. The programmable memory system as claimed in claim 2, wherein each said associated first programmable logic device is responsive to pre-determined lower physical memory address bit locations having bit values used in generating said select signal for enabling a substantially even distribution of accesses across said one or more memory storage structures.

8. The programmable memory system as claimed in claim 2, wherein each said associated first programmable logic device is responsive to pre-determined higher physical memory address bit locations used for assigning a memory region in said one or more memory structures to one or more processors.

9. The programmable memory system as claimed in claim 2, wherein each said associated first programmable logic device output select signal comprises an asserted bit value output, said second logic device for concatenating one or more said bit value outputs from said associated first programmable logic devices and generating a bit vector comprising bit values output from associated first programmable logic devices for use as said address signal used to select a memory storage structure.

10. The programmable memory system as claimed in claim 2, wherein said one or more memory storage structures comprises a single cache memory system, a multi-level memory system or a main memory storage system for a processor device.

11. A method for accessing a shared memory provided in a computing system having one or more processor devices, said shared memory organized as a plurality of memory storage structures having addressable locations for storing data for said one or more processor devices, said method comprising:

receiving, at a first logic device associated with each one or more processor device, a physical memory address signal and determining bit values at select bit address locations of said received physical memory address signal;

generating, at said first logic device, a respective select signal corresponding to one of said one or more memory storage structures based upon said determined address bit values selected; and

,

generating, at a second logic device, in response to a corresponding select signals, an address signal used for selecting a memory storage structure for a processor device access,

wherein each processor device of said computing system is enabled memory storage access distributed across said one or more memory storage structures.

12. The method as claimed in claim 11, further comprising:

using unselected bit values of said received physical memory address signal to enable processor device access to memory locations within a selected memory storage structure.

13. The method as claimed in claim 12, further comprising:

programming said first logic device to provide a single processor device exclusive access to a single memory storage structure upon receipt of predetermined selected address bit values at pre-determined physical memory address bit locations.

14. The method as claimed in claim 12, further comprising:

programming said first logic device to respond to pre-determined lower physical memory address bit locations used in generating said select signal for providing a single processor device with a substantially even distribution of accesses across said one or more memory storage structures.

15. The method as claimed in claim 12, further comprising:

programming said first logic device to respond to pre-determined higher physical memory address bit locations used for assigning a memory region in said one or more memory structures to one or more processors.

16. The method as claimed in claim 12, wherein each said associated first programmable logic device output select signal comprises an asserted bit value output,

said second logic device for concatenating one or more said bit value outputs from said associated first programmable logic devices and generating a bit vector comprising bit values output from associated first programmable logic devices for use as said address signal.

17. A multiprocessor computing system comprising one or more processor devices and a shared memory comprising one or more memory storage structures having addressable locations for storing data for said one or more processor devices, said system comprising:

one or more first logic devices associated with a respective said one or more processor devices, each first logic device for receiving physical memory address signals and generating a respective select signal corresponding to one of said one or more memory storage structures upon receipt of pre-determined address bit values at selected physical memory address bit locations;

a second logic device responsive to said corresponding respective select signals for generating an address signal used for selecting a memory storage structure for processor access,

wherein each processor device of said computing system is enabled memory storage access distributed across said one or more memory storage structures.

18. The multiprocessor computing system as claimed in claim 17, wherein unselected bit values of said received physical memory address signal are used to enable processor device access to memory locations within a selected memory storage structure.

19. The multiprocessor computing system as claimed in claim 18, wherein said selected address bit values are programmable for enabling a single processor exclusive access to a single memory storage structure.

20. The multiprocessor computing system as claimed in claim 18, wherein each said associated first programmable logic device includes a multiplexer device programmed to respond to pre-determined bit values at pre-determined physical memory address bit locations.

21. The multiprocessor computing system as claimed in claim 17, wherein each said associated first programmable logic device implements logic for applying a hash function to said physical memory address signals.

22. The programmable memory system as claimed in claim 21, wherein each said associated first programmable logic device comprises an XOR reduction tree for applying a hash function, an output of each said XOR reduction tree generating said memory storage structure select signal.

23. The multiprocessor computing system as claimed in claim 18, wherein each said associated first programmable logic device output select signal comprises an asserted bit value output,

said second logic device for concatenating one or more said bit value outputs from said associated first programmable logic devices and generating a bit vector comprising bit values output from associated first programmable logic devices for use as said address signal used to select a memory storage structure.

24. An apparatus for enabling one or more processor devices access to shared memory in a computing environment, the shared memory including one or more memory storage structures having addressable locations for storing data, said apparatus comprising:

one or more first logic devices associated with a respective a processor device, each said first logic device for receiving a different subset of address bit signals comprising said physical memory address;

gating means associated with each said one or more first logic devices and each programmable for gating off some or all selected bits of each different subset of address bit signals received at each said first logic device, wherein remaining ungated bits correspond to a desired shared memory storage structure to be accessed, each respective said one or more first logic devices receiving said remaining ungated bits for applying a hash function to said remaining ungated bits and generating a respective memory storage structure select signal; and

,

a second logic device responsive to each the respective select signal for generating an address signal used for selecting a memory storage structure for processor access,

the system enabling each processor device of a computing environment memory storage access distributed across the one or more memory storage structures.

25. The apparatus as claimed in claim 24, wherein each said associated first logic devices comprises an XOR reduction tree for applying said hash function, an output of each said XOR reduction tree comprising said generated memory storage structure select signal.

26. The apparatus as claimed in claim 25, wherein each said gating means associated with each said one or more first logic devices comprises a column of logic gates receiving a respective different subset of address bit signals and receiving a control signal for controlling gating off said some or all selected bits.

27. The apparatus as claimed in claim 26, wherein each said logic gates include an AND gate.

28. The apparatus as claimed in claim 24, further comprising:

a means for receiving unselected or gated off bit values of each different subset of address bit signals of the received physical memory address and for generating an offset bit vector signal used to access to memory locations within a selected memory storage structure.

29. A method for enabling one or more processor devices access to shared memory in a computing environment, the shared memory including one or more memory storage structures having addressable locations for storing data, said method comprising:

receiving, at one or more first logic devices associated with a respective a processor device, a different subset of address bit signals comprising said physical memory address;

gating some or all selected bits of each different subset of address bit signals received at each said first logic device, wherein remaining ungated bits correspond to a desired shared memory storage structure to be accessed,

applying, at said one or more first logic devices, a hash function to said remaining ungated bits and generating a respective memory storage structure select signal; and

,

generating, at a second logic device, in response to a corresponding select signals, an address signal used for selecting a memory storage structure for a processor device access,

wherein each processor device of said computing system is enabled memory storage access distributed across said one or more memory storage structures.

30. The method as claimed in claim 29, wherein each said associated first logic devices comprises an XOR reduction tree for applying said hash function, an output of each said XOR reduction tree comprising said generated memory storage structure select signal.

31. The method as claimed in claim 29, further comprising:

receiving at a control signal for controlling gating of said some or all selected bits at said each associated said one or more first logic devices.

32. The method as claimed in claim 29, further comprising:

using unselected or gated off bit values of each different subset of address bit signals of the received physical memory address to enable processor device access to memory locations within a selected memory storage structure.