CACHE FOR A MULTI THREAD AND MULTI CORE SYSTEM AND METHODS THEREOF

• US 20090006729A1
• Filed: 06/28/2007
• Published: 01/01/2009
• Est. Priority Date: 06/28/2007
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Cheng, Scott, Piazza, Thomas A., Dwyer, Michael K.
• Granted Patent: US 8,171,225 B2
• Time in Patent Office: Days
• US Class Current: 711/104
• CPC Class Codes: G06F 12/0859 with reload from main memory

Abstract

According to one embodiment, the present disclosure generally provides a method for improving the performance of a cache of a processor. The method may include storing a plurality of data in a data Random Access Memory (RAM). The method may further include holding information for all outstanding requests forwarded to a next-level memory subsystem. The method may also include clearing information associated with a serviced request after the request has been fulfilled. The method may additionally include determining if a subsequent request matches an address supplied to one or more requests already in-flight to the next-level memory subsystem. The method may further include matching fulfilled requests serviced by the next-level memory subsystem to at least one requester who issued requests while an original request was in-flight to the next level memory subsystem. The method may also include storing information specific to each request, the information including a set attribute and a way attribute, the set and way attributes configured to identify where the returned data should be held in the data RAM once the data is returned, the information specific to each request further including at least one of thread ID, instruction queue position and color. The method may additionally include scheduling hit and miss data returns. Of course, various alternative embodiments are also within the scope of the present disclosure.

Claims

1. A cache for a processor, the cache comprising:

a plurality of instruction queues configured to handle at least one out-of-order instruction return;

a data Random Access Memory (RAM) capable of storing a plurality of data;

a tag RAM capable of storing memory addresses and data of the plurality of data stored in the data RAM;

an in-flight RAM capable of

holding information for all outstanding requests forwarded to a next-level memory subsystem;

clearing information associated with a serviced request after the request has been fulfilled;

determining if a subsequent request matches an address supplied to one or more requests already in-flight to the next-level memory subsystem;

matching fulfilled requests serviced by the next-level memory subsystem to at least one requester who issued requests while an original request was in-flight to the next-level memory subsystem; and

storing information specific to each request, the information including a set attribute and a way attribute, the set and way attributes configured to identify where the returned data should be held in the data RAM once the data is returned, the information specific to each request further including at least one of thread ID, instruction queue position and color; and

an arbiter for scheduling hit and miss data returns.

2. The cache of claim 1, wherein the cache is capable of providing access to the plurality of data stored in the data RAM to the plurality of cores.

3. The cache of claim 1, wherein the data RAM reduces a latency of the plurality of data stored in the data RAM.

4. The cache of claim 1, wherein the at least one of thread ID, instruction queue position and color may be supplied back to the requester once the request is fulfilled.

5. The cache of claim 4, wherein the cache returns data to the plurality of threads in a single clock time.

6. The cache of claim 1, further comprising an EU interface comprising a color bit for determining the relevance of returned data at the time the data is returned.

7. The cache of claim 6, wherein the EU interface improves a performance of the cache of the processor having a low hit ratio.

8. A multi core and a multi thread system, the system comprising:

a plurality of cores; and

a cache connected to the plurality of cores, the cache comprising

a plurality of instruction queues configured to handle at least one out-of-order instruction return;

a data Random Access Memory (RAM) capable of storing a plurality of data;

a tag RAM capable of storing memory addresses and data of the plurality of data stored in the data RAM;

an in-flight RAM capable of

holding information for all outstanding requests forwarded to a next-level memory subsystem;

clearing information associated with a serviced request after the request has been fulfilled;

determining if a subsequent request matches an address supplied to one or more requests already in-flight to the next-level memory subsystem;

matching fulfilled requests serviced by the next-level memory subsystem to at least one requester who issued requests while an original request was in-flight to the next-level memory subsystem; and

storing information specific to each request, the information including a set attribute and a way attribute, the set and way attributes configured to identify where the returned data should be held in the data RAM once the data is returned, the information specific to each request further including at least one of thread ID, instruction queue position and color; and

an arbiter for scheduling hit and miss data returns.

9. The system of claim 8, wherein the cache is capable of providing access to the plurality of data stored in the data RAM to the plurality of cores.

10. The system of claim 8, wherein the data RAM reduces a latency of the plurality of data stored in the data RAM.

11. The system of claim 8, wherein at least one of the thread ID, instruction queue position, and color may be supplied back to the requester once the request is fulfilled.

12. The system of claim 11, wherein the cache provides access of the instruction data to the plurality of threads in a single clock time.

13. The system of claim 8, further comprising an EU interface comprising a color bit for determining the relevance of returned data at the time the data is returned and allowing speculative requests by the EUs.

14. The system of claim 13, wherein the EU interface improves a performance of the cache of the processor having a low hit ratio.

15. A method for improving performance of a cache of a processor, the method comprising:

storing a plurality of data in a data Random Access Memory (RAM);

storing memory addresses of the plurality of data stored in the data RAM in a tag RAM;

holding information for all outstanding requests forwarded to a next-level memory subsystem;

clearing information associated with a serviced request after the request has been fulfilled;

determining if a subsequent request matches an address supplied to one or more requests already in-flight to the next-level memory subsystem;

matching fulfilled requests serviced by the next-level memory subsystem to at least one requestor who issued requests while an original request was in-flight to the next-level memory subsystem;

storing information specific to each request, the information including a set attribute and a way attribute, the set and way attributes configured to identify where the returned data should be held in the data RAM once the data is returned, the information specific to each request further including at least one of thread ID, instruction queue position and color; and

scheduling hit and miss data returns.

16. The method of claim 15, wherein the cache is capable of providing access of the plurality of data stored in the data RAM to the plurality of cores.

17. The method of claim 15, wherein the data RAM reduces a latency of the plurality of data stored in the data RAM.

18. The method of claim 15, wherein the thread ID and color may be supplied back to the requestor once the request is fulfilled

19. The method of claim 18, wherein the cache provides access of the instruction data to the plurality of threads in a single clock time.

20. The method of claim 15, further comprising an EU interface comprising a color bit for reducing a latency in case of the jump instruction.