PROGRAMMABLE PARTITIONING FOR HIGH-PERFORMANCE COHERENCE DOMAINS IN A MULTIPROCESSOR SYSTEM

• US 20090006769A1
• Filed: 06/26/2007
• Published: 01/01/2009
• Est. Priority Date: 06/26/2007
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Blumrich, Matthias A., Salapura, Valentina
• Granted Patent: US 7,877,551 B2
• Time in Patent Office: Days
• US Class Current: 711/146
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means

Abstract

A multiprocessor computing system and a method of logically partitioning a multiprocessor computing system are disclosed. The multiprocessor computing system comprises a multitude of processing units, and a multitude of snoop units. Each of the processing units includes a local cache, and the snoop units are provided for supporting cache coherency in the multiprocessor system. Each of the snoop units is connected to a respective one of the processing units and to all of the other snoop units. The multiprocessor computing system further includes a partitioning system for using the snoop units to partition the multitude of processing units into a plurality of independent, memory-consistent, adjustable-size processing groups. Preferably, when the processor units are partitioned into these processing groups, the partitioning system also configures the snoop units to maintain cache coherency within each of said groups.

Claims

1. A multiprocessor computing system comprising:

a multitude of processing units, each of the processing units including a local cache;

a multitude of snoop units for supporting cache coherency in the multiprocessor system, each of the snoop units being connected to a respective one of the processing units and to all of the other snoop units; and

a partitioning system for using the snoop units to partition the multitude of processing units into a plurality of independent, memory-consistent, adjustable-size groups.

2. A multiprocessor computing system according to claim 1, wherein the partitioning system configures the snoop units into said groups while maintaining cache coherency within each of said groups.

3. A multiprocessor computing system according to claim 2, wherein, in use, data packets resulting from memory access requests are sent from the processing units to the snoop units, each of the snoop units including a packet processor for processing said data packets, and wherein:

the partitioning system includes a multitude of control mechanisms, and each of said control mechanisms is associated with one of the snoop units; and

each of the control mechanisms blocks the associated snoop units from processing selected ones of said data packets.

4. A multiprocessor computing system according to claim 3, wherein, when one of said snoop units is in a defined one of said plurality of groups, the control mechanism associated with said one of the snoop units blocks said associated snoop unit from processing data packets from processing units outside said defined one of said plurality of groups.

5. A multiprocessor computing system according to claim 4, wherein the control mechanism associated with said one of the snoop units does not block said one of the snoop units from processing data packets coming from processing units within said defined one of said plurality of groups.

6. A multiprocessor computing system according to claim 5, wherein each of the control mechanisms includes programmable registers for identifying which data packets are to be processed by the associated snoop unit and which data packets are to be blocked from being processed by the associated snoop unit.

7. A multiprocessor computing system according to claim 6, wherein some of the data packets are accompanied by data valid signals, and said each of the control mechanisms further includes a gate for selectively passing data valid signals to the packet processor of the associated snoop unit.

8. A multiprocessor computing system according to claim 7, in each of the control mechanisms, control values from the register of the control mechanism are applied to the gate of the control mechanism to determine which data valid signals are passed to the packet processor of the associated snoop unit.

9. A multiprocessor computing system according to claim 8, wherein the data valid signals are sent from the snoop units to the snoop units, and when each snoop unit receives selected ones of the data valid signals, said each snoop unit returns said selected ones of the data valid signals to the snoop units that sent said selected ones of the data valid signals.

10. A multiprocessor computing system according to claim 9, wherein each of the snoop units includes one or more snoop filters to process data packets and present a reduced number of data packets to the processor.

11. A method for logically partitioning a multiprocessor computing system, said multiprocessor computing system comprising a multitude of processing units, each of the processing units including a local cache, and the multiprocessor computing system further comprising a multitude of snoop units for supporting cache coherency in the multiprocessor computing system, each of the snoop units being connected to a respective one of the processing units and to all of the other snoop units of the multiprocessor computing system, the method comprising the steps of:

transmitting data packets resulting from memory access requests from the processing units to the snoop units; and

using the snoop units to partition the multitude of processing units into a plurality of independent, memory-consistent, adjustable-size groups.

12. A method according to claim 11, wherein the using step includes the step of configuring the snoop units into said groups to maintain cache coherency within each of said groups.

13. A method according to claim 12, wherein each of the snoop units includes a packet processor for processing said data packets, and wherein:

the using step includes the step of blocking the packet processors of selected ones of the snoop units from processing selected ones of said data packets.

14. A method according to claim 13, wherein the blocking step includes the step of blocking snoop units within a defined one of the groups from processing data packets coming from processing units outside said defined one of said plurality of groups.

15. A method according to claim 14, wherein the using step includes the step of not blocking any of the snoop units within said defined one of said plurality of groups from processing data packets from processing units within said defined one of said plurality of groups.

16. A method according to claim 15, wherein each of the snoop units includes programmable registers for identifying which data packets are to be processed by the snoop unit and which data packets are to be blocked from being processed by the snoop unit.

17. A method according to claim 15, wherein each of the snoop units includes one or more snoop filters to process data packets and present a reduced number of data packets to the processors.

19. A program storage device according to claim 17, wherein the using step includes the step of configuring the snoop units into said groups to maintain cache coherency within each of said groups.

18. A program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform method steps for logically partitioning a multiprocessor computing systems, said multiprocessor computing system comprising a multitude of processing units, each of the processing units including a local cache, and the multiprocessor computing system further comprising a multitude of snoop units for supporting cache coherency in the multiprocessor computing system, each of the snoop units being connected to a respective one of the processing units and to all of the other snoop units of the multiprocessor computing system, said method steps comprising the steps of:

transmitting data packets from the processor units to the snoop units; and

using the snoop units to partition the multitude of processor units into a plurality of independent, memory-coherent adjustable-size groups.

20. A program storage device according to claim 18, wherein the using step includes the steps of:

blocking snoop units within a defined one of the groups from processing data packets from processing units outside said defined one of said plurality of groups; and

not blocking any of the snoop units within said defined one of said plurality of groups from processing data packets from processing units within said defined one of said plurality of groups.