SYSTEM AND METHOD FOR PROVIDING A HIGH FAULT TOLERANT MEMORY SYSTEM

• US 20090006900A1
• Filed: 06/28/2007
• Published: 01/01/2009
• Est. Priority Date: 06/28/2007
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gower, Kevin C., Lastras-Montano, Luis A., Dewkett, Thomas J., O'Connor, James A., Clarke, William J., Dell, Timothy J., Alves, Luiz C.
• Granted Patent: US 8,041,989 B2
• Time in Patent Office: Days
• US Class Current: 714/42
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/4401 for self repair
• CPC Class Codes: G11C 29/81 using a hierarchical redundancy scheme
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports

Abstract

A system and method for providing a high fault tolerant memory system. The system includes a memory system having a memory controller, a plurality of memory modules and a mechanism. The plurality of memory modules are in communication with the memory controller and with a plurality of memory devices. The plurality of memory devices include at least one spare memory device for providing memory device sparing capability. The mechanism is for detecting that one of the memory modules has failed possibly coincident with a memory device failure on an other of the memory modules. The mechanism allows the memory system to continue to run unimpaired in the presence of the memory module failure and the possible memory device failure.

Claims

1. A memory system comprising:

a memory controller;

a plurality of memory modules in communication with the memory controller and with a plurality of memory devices, the plurality of memory devices including at least one spare memory device for providing memory device sparing capability; and

a mechanism for detecting that one of the memory modules has failed possibly coincident with a memory device failure on an other of the memory modules, and for allowing the memory system to continue to run unimpaired in the presence of the memory module failure and the possible memory device failure.

2. The memory system of claim 1 wherein a memory module includes one or more memory devices utilized for error detection and correction across the memory module.

3. The memory system of claim 1 wherein substantially all of the memory devices on one of the memory modules are utilized for error detection and correction across the memory modules.

4. The memory system of claim 1 wherein the detecting that one of the memory modules has failed includes testing each of the memory modules to determine whether the memory module has a correctable error.

5. The memory system of claim 1 wherein the plurality of memory modules include five memory modules in communication with the memory controller via five different channels, the five memory modules including four memory modules having one memory device utilized for error detection and correction across the memory modules and one memory device utilized as the spare memory device.

6. The memory system of claim 1 wherein the mechanism utilizes a RAID-3 error correction code applied to the memory devices organized in a row across multiple memory modules and the remaining redundant symbols check the information stored on two or more of the memory modules.

7. The memory system of claim 1 wherein the mechanism further detects an additional memory device failure.

8. The memory system of claim 1 wherein the mechanical packaging of the memory system is adapted to allow replacement of one of the memory modules concurrent with system operation.

9. The memory system of claim 1 wherein the mechanical packaging of the memory system is adapted to allow replacement of one or more of the memory devices concurrent with system operation.

10. A memory controller comprising:

an interface to a plurality of memory modules, the modules in communication with a plurality of memory devices, the plurality of memory devices including at least one spare memory device for providing memory device sparing capability; and

a mechanism for detecting that one of the memory modules has failed possibly coincident with a memory device failure on an other of the memory modules, and for allowing the memory system to continue to run unimpaired in the presence of the memory module failure and the possible memory device failure.

11. The memory controller of claim 10 wherein a memory module includes one or more memory devices utilized for error detection and correction across the memory module.

12. The memory controller of claim 10 wherein the detecting that one of the memory modules has failed includes testing each of the memory modules to determine whether the memory module has a correctable error.

13. The memory controller of claim 10 wherein the plurality of memory modules includes five memory modules in communication with the memory controller via five different channels, the five memory modules including four memory modules having one memory device utilized for error detection and correction across the memory modules and one memory device utilized as the spare memory device.

14. The memory controller of claim 10 wherein the mechanism utilizes a RAID-3 error correction code applied to the memory devices organized in a row across multiple memory modules and the remaining redundant symbols check information stored on two or more of the memory modules.

15. The memory controller of claim 10 wherein the mechanism further detects an additional memory device failure.

16. A method for detecting and correcting errors in a memory system, the method comprising:

determining if only a single symbol error exists in the memory system, the memory system including a plurality of memory modules having memory devices including at least one spare memory device for providing memory device sparing capability, the memory modules accessed in unison in response to memory commands;

correcting the single symbol error in response to determining that the single symbol error is the only error that exists in the memory system;

correcting for a possible memory module failure using the RAID-3 error correction code in response to determining that the error is not a single symbol error; and

correcting for errors remaining in the memory system after the correcting for the possible memory module failure.

17. The method of claim 16 further comprising identifying failing memory devices by tracking previous persistent failures, and copying the information from a persistently failing memory device to one of the spare memory devices.

18. The method of claim 17, wherein the spare memory device in the memory module containing the persistently failing memory device is given preference for being utilized in the copying, and a spare memory device in an other memory module is chosen for the copying if no spare memory device in the memory module is available.

19. The method of claim 17, further comprising identifying sections of failing memory devices by tracking previous persistent failures and if the section of a failing memory device is smaller than a full memory device, copying only the failing section to a spare chip.

20. The method of claim 16 wherein the memory module failure includes a failure of any failing device that is used in communication between the memory devices and a memory controller, even if the failing device is physically not present in the failing memory module.