Techniques For Generating Bit Reliability Information In A Post-Processor Using An Error Correction Constraint

• US 20090006931A1
• Filed: 06/29/2007
• Published: 01/01/2009
• Est. Priority Date: 06/29/2007
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co), Western Digital Technologies Incorporated (Western Digital Corporation)
• Original Assignee: Hitachi Global Storage Technologies Netherlands BV (Western Digital Corporation)
• Inventors: Blaum, Mario, Wilson, Bruce Alexander, Lee, Yuan Xing, Li, Zongwang, Djurdjevic, Ivana, Lakovic, Ksenija, Galbraith, Richard Leo, Oenning, Travis Roger
• Granted Patent: US 8,037,394 B2
• Time in Patent Office: Days
• US Class Current: 714/799
• CPC Class Codes: G11B 20/10046 filtering or equalising, e.g. setting the tap weights of an FIR filter
• CPC Class Codes: G11B 20/1833 by adding special lists or symbols to the coded information G11B20/1806, G11B20/1866 take precedence
• CPC Class Codes: G11B 2020/185 using an low density parity check [LDPC] code
• CPC Class Codes: G11B 2020/1863 wherein the Viterbi algorithm is used for decoding the error correcting code
• CPC Class Codes: H03M 13/1102 Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
• CPC Class Codes: H03M 13/2957 Turbo codes and decoding
• CPC Class Codes: H03M 13/6343 Error control coding in combination with techniques for partial response channels, e.g. recording

Abstract

Techniques are provided that generate bit reliabilities for a detected sequence. A detector generates the detected sequence. According to one embodiment, a post-processor finds a first set of combinations of one or more error events in the detected sequence satisfying a complete set or a subset of error correction constraints corresponding to the first bit value, finds a second set of combinations of one or more error events in the detected sequence satisfying a complete set or a subset of error correction constraints corresponding to the second bit value, selects a first most likely combination of one or more events of the first set and a second most likely combination of one or more events of the second set, and generates a bit reliability based on the first and the second most likely values.

Claims

1. A system for generating bit reliabilities, the system comprising:

a detector that generates a detected sequence; and

a post-processor that finds a first set of combinations of at least one error event in the detected sequence satisfying error correction constraints corresponding to a first bit value, finds a second set of combinations of at least one error event in the detected sequence satisfying error correction constraints corresponding to a second bit value, selects a first most likely error event from the first set and a second most likely error event from the second set, and generates a bit reliability based on the first and the second most likely error events.

2. The system defined in claim 1 further comprising:

a list compiler that generates a list of most likely error events for multiple syndrome values based on error correction constraints, wherein the list of most likely error events is transmitted to the post-processor.

3. The system defined in claim 2 wherein the post-processor selects a first error event and a second companion error event, wherein the second companion error event is an error event in the list of most likely error events that does not overlap the first error event, such that the first and the second companion error events together drive a syndrome of the detected sequence to zero.

4. The system defined in claim 2 wherein the list of most likely error events generated by the list compiler comprises error events for multiple syndrome values of a block in the detected sequence.

5. The system defined in claim 4 wherein the list of most likely error events generated by the list compiler comprises at least two most likely non-overlapping error events that drive the syndrome of the block in the detected sequence to zero.

6. The system defined in claim 1 wherein the post-processor is a soft-input-soft-output post-processor.

7. The system defined in claim 1 wherein the post-processor comprises:

error event filters that store multi-bit error events; and

qualifiers that determine if each of the multi-bit error events is qualified based on the detected sequence.

8. The system defined in claim 3 wherein the post-processor comprises:

latches that store probability values for the error events at different bit locations; and

qualifiers that determine if an error event is qualified based on the second companion error event.

9. The system defined in claim 8 wherein the post-processor further comprises:

a selector block that selects a most likely one of the probability values corresponding to error events that flip a current bit from among the probability values stored in the latches.

10. The system defined in claim 9 wherein the post-processor further comprises:

a non-overlapping zero syndrome block that identifies a most likely error event from the list of most likely error events such that the most likely error event causes a syndrome of a block in the detected sequence to be driven to zero and does not overlap a current bit;

an adder that receives an output of the selector block and an output of the non-overlapping zero syndrome block; and

a multiplier that multiplies an output of the adder by a bit from the detected sequence, the bit having a value of +1 for a binary 1 and −

1 for a binary 0.

11. The system defined in claim 1 wherein the detector is a Viterbi detector.

12. A method for generating bit reliabilities using a post-processor, the method comprising:

receiving a detected sequence from a detector;

locating a first set of combinations of at least one error event in the detected sequence satisfying error correction constraints corresponding to a first bit value;

locating a second set of combinations of at least one error event in the detected sequence satisfying error correction constraints corresponding to a second bit value;

selecting a first most likely error event from the first set and a second most likely error event from the second set; and

generating a bit reliability based on the first and the second most likely error events.

13. The method defined in claim 12 further comprising:

generating a list of most likely error events for multiple syndrome values based on error correction constraints.

14. The method defined in claim 13 wherein locating the first set of combinations of at least one error event in the detected sequence satisfying error correction constraints corresponding to the first bit value further comprises selecting a first error event and a second companion error event, wherein the second companion error event is an error event in the list of most likely error events that does not overlap the first error event, such that the first and the second companion error events together drive a syndrome of the detected sequence to zero.

15. The method defined in claim 13 wherein the list of most likely error events comprises error events for multiple syndrome values of a block in the detected sequence.

16. The method defined in claim 15 wherein the list of most likely error events comprises at least two most likely non-overlapping error events that drive a syndrome of the block in the detected sequence to zero.

17. The method defined in claim 12 wherein the post-processor is a soft-input-soft-output post-processor.

18. A data storage device that generates bit reliabilities, the data storage device comprising:

a detector that generates a detected sequence;

a list compiler that generates a list of most likely error events for multiple syndrome values using error correction constraints; and

a post-processor that finds a first set of combinations of at least one error event in the detected sequence satisfying error correction constraints corresponding to a first bit value, finds a second set of combinations of at least one error event in the detected sequence satisfying error correction constraints corresponding to a second bit value, selects a first most likely error event from the first set and a second most likely error event from the second set, and generates a bit reliability based on the first and the second most likely error events.

19. The data storage device defined in claim 18 wherein the post-processor selects a first error event and a second companion error event, wherein the second companion error event is an error event in the list of most likely error events that does not overlap the first error event, such that the first and the second companion error events together drive a syndrome of the detected sequence to zero.

20. The data storage device defined in claim 18 wherein the list of most likely error events generated by the list compiler comprises error events for multiple syndrome values of a block in the detected sequence based on a parity constraint.