Method and apparatus for schema validation

• US 20090006943A1
• Filed: 06/28/2007
• Published: 01/01/2009
• Est. Priority Date: 06/28/2007
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Matheson, Jack, Tsoi, Howard
• Granted Patent: US 7,865,823 B2
• Time in Patent Office: Days
• US Class Current: 715/234
• CPC Class Codes: G06F 40/226 Validation

Abstract

In one embodiment, the invention may include receiving an XML schema and document with first, second, third, and fourth nodes. The second and third nodes may descend from the first node. The fourth node may descend from the second node. The third and fourth nodes may be simultaneously validated.

Claims

1. A method comprising:

receiving an XML schema;

receiving a parsed XML document that includes a parent node, a first child node, a second child node, and a grandchild node;

validating the first child node; and

simultaneously validating the second child node and the grandchild node;

wherein the first child node directly descends from the parent node, the second child node directly descends from the parent node, and the grandchild node directly descends from the first child node.

2. The method of claim 1, further comprising:

validating the second child node with a first processor core; and

validating the grandchild node with a second processor core;

wherein a first processor includes the first processor core and the second processor core.

3. The method of claim 1, further comprising validating the second child node via a first thread and validating the grandchild node via a second thread, the first thread and the second thread validated using a single core processor.

4. The method of claim 1, further comprising:

validating the second child node via a first finite state machine; and

validating the grandchild node via a second finite state machine.

5. The method of claim 4, further comprising validating the parent node via a host finite state machine, the host finite state machine including the first finite state machine and the second finite state machine.

6. The method of claim 1, further comprising:

validating the first child node with a first processor core; and

validating the second child node with a second processor core;

wherein a first processor includes the first processor core and the second processor core.

7. The method of claim 1, further comprising completing validation of the second child node after completing validation of the grandchild node.

8. An apparatus comprising:

a memory to receive a parseable XML document that includes a parent node, a first child node, and a second child node, the first child node descending from the parent node and the second child node descending from the parent node; and

a processor, to couple to the memory, to simultaneously validate the first child node and the second child node based on an XML schema.

9. The apparatus claim 8, wherein the processor is to validate the first child node with a first processor core and validate the second child node with a second processor core;

the processor to include the first processor core and the second processor core.

10. The apparatus of claim 8, wherein the processor is to validate the first child node via a first thread and validate the second child node via a second thread, the processor to include only a single core.

11. The apparatus of claim 8, wherein the processor is to validate the first child node via a first finite state machine and validate the second child node via a second finite state machine.

12. The apparatus of claim 11, wherein the processor is to validate the parent node via a host finite state machine, the host finite state machine including the first finite state machine and the second finite state machine.

13. The apparatus of claim 8, wherein the processor is to:

validate the first child node with a first processor core; and

validate the parent node with a second processor core;

wherein the processor includes the first processor core and the second processor core.

14. The apparatus of claim 8, wherein the processor is to complete validation of the first child node after completing validation of the second child node.