METHOD AND SYSTEM FOR IMPLEMENTING CACHED PARAMETERIZED CELLS

• US 20090007031A1
• Filed: 06/27/2007
• Published: 01/01/2009
• Est. Priority Date: 06/27/2007
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Lamant, Gilles S.C., Ginetti, Arnold, Bishop, Randy
• Granted Patent: US 7,971,175 B2
• Time in Patent Office: Days
• US Class Current: 716/136
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

Parameterized cells are cached and provided by the plug-in to increase the speed and efficiency of an application for circuit design. This allows source design to be read-interoperable and also enables some basic write-interoperability in the source design.

Claims

1. A method for providing parameterized cells (pcells) to a third party application, comprising:

determining whether a persistent pcell includes the desired pcell information;

storing the pcell information in a file if the pcell is stored as the persistent pcell;

evaluating the pcell at a remote design platform if persistent pcell is not available for retrieval;

providing the evaluated pcell to the third party application; and

storing the evaluated pcell for future retrieval.

2. The method of claim 1, wherein files of the same pcells are stored in the same binary file cache.

3. The method of claim 1, wherein the remote design platform is coupled to a pcell evaluator.

4. The method of claim 3, wherein a reduced pcell plug-in is communicatively coupled to the third party application and the pcell evaluator.

5. The method of claim 1 wherein the design plateform is Virtuoso.

6. A method for providing parameterized cells (pcells) to a third party application, comprising:

determining whether a persistent pcell includes the desired pcell information; and

storing the pcell information in a file if the pcell is stored as the persistent pcell, wherein the third party application includes read access of the persistent pcell and does not include write access.

7. The method of claim 6, wherein files of the same pcells are stored in the same binary file cache.

8. The method of claim 6, wherein the third party application is coupled to a reduced pcell plug-in, which is unable to evaluate a pcell.

9. The method of claim 6, further comprising invoking a complete evaluator to populate a file and store for future retrieval.

10. The method of claim 9, wherein the evaluator includes a Virtuoso evaluator or any tool containing Virtuoso'"'"'s evaluator.

11. A method for providing parameterized cells (pcells) to a design platform, comprising:

determining whether the pcell is stored as a persistent pcell;

evaluating the pcell if persistent pcell is not available for retrieval; and

storing the evaluated pcell for future retrieval.

12. The method of claim 11, wherein files of the same pcells are stored in the same binary file cache.

13. The method of claim 11, wherein the design platform is coupled to a pcell evaluator.

14. The method of claim 11 wherein the design plateform is Virtuoso.

15. An apparatus, comprising:

means for determining whether the pcell is stored as a persistent pcell;

means for evaluating the pcell if persistent pcell is not available for retrieval; and

means for storing the evaluated pcell for future retrieval.

16. A computer program product embodied on computer readable medium, the computer readable medium having stored thereon a sequence of instructions which, when executed by a processor, causes the processor to execute a method for specifying property values of a hierarchical circuit design, the method comprising:

determining whether the pcell is stored as a persistent pcell;

evaluating the pcell if persistent pcell is not available for retrieval; and

storing the evaluated pcell for future retrieval.

17. An apparatus, comprising:

means for determining whether a persistent pcell includes the desired pcell information; and

means for storing the pcell information in a file if the pcell is stored as the persistent pcell, wherein the third party application includes read access of the persistent pcell and does not include write access.

18. A computer program product embodied on computer readable medium, the computer readable medium having stored thereon a sequence of instructions which, when executed by a processor, causes the processor to execute a method for specifying property values of a hierarchical circuit design, the method comprising:

determining whether a persistent pcell includes the desired pcell information; and

storing the pcell information in a file if the pcell is stored as the persistent pcell, wherein the third party application includes read access of the persistent pcell and does not include write access.

19. An apparatus, comprising:

means for determining whether a persistent pcell includes the desired pcell information;

means for storing the pcell information in a file if the pcell is stored as the persistent pcell;

means for evaluating the pcell at a remote design platform if persistent pcell is not available for retrieval;

means for providing the evaluated pcell to the third party application; and

means for storing the evaluated pcell for future retrieval.

20. A computer program product embodied on computer readable medium, the computer readable medium having stored thereon a sequence of instructions which, when executed by a processor, causes the processor to execute a method for specifying property values of a hierarchical circuit design, the method comprising:

determining whether a persistent pcell includes the desired pcell information;

storing the pcell information in a file if the pcell is stored as the persistent pcell;

evaluating the pcell at a remote design platform if persistent pcell is not available for retrieval;

providing the evaluated pcell to the third party application; and

storing the evaluated pcell for future retrieval.