Accurate Parasitic Capacitance Extraction for Ultra Large Scale Integrated Circuits

• US 20090007035A1
• Filed: 10/01/2007
• Published: 01/01/2009
• Est. Priority Date: 06/29/2007
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Gwan Sin, Su, Ke-Ying, Ho, Chia-Ming, Chen, Chien-Wen
• Granted Patent: US 7,818,698 B2
• Time in Patent Office: Days
• US Class Current: 716/106
• CPC Class Codes: G01R 31/2853 Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.

Claims

1. A method of electronically generating a technology file for extracting parasitic capacitance in an integrated circuit layout comprising the steps of:

providing a plurality of contact/via capacitance test structures, having substantially similar dimensions and different contact/via configurations;

measuring parasitic contact/via capacitance on said plurality of test structures;

creating an effective contact/via width table, wherein each element of said table corresponds to a polygon-shaped contact/via and has a calculated parasitic capacitance matching to that of one of said plurality of test structures; and

generating a capacitance table corresponding to said effective contact/via width table.

2. The method of claim 1, wherein said test structures are MOS transistors, having substantially similar dimensions and different contact configurations.

3. The method of claim 1, wherein said contact/via configurations include contacts/vias having cylindrical shapes and variations in size.

4. The method of claim 2, wherein said contact configurations have contact-to-contact and contact-to-gate-electrode distances that are each multiples of minimum design rule distances, respectively.

5. The method of claim 1, wherein each element of said effective contact/via width table corresponds to a contact/via configuration having a square-shaped contact/via.

6. The method of claim 1, wherein said step of creating said effective contact/via width table includes:

providing a measured value of contact/via parasitic capacitance;

preparing a process characterization file, said process characterization file including a trial value of a contact/via area;

calculating contact/via parasitic capacitance value by making use of a field solver with said process characterization file; and

comparing the calculated capacitance/via value with the measured contact/via parasitic capacitance value to determine an effective contact width.

7. The method of claim 6, wherein said field solver has a 3-D accuracy.

8. The method of claim 1, wherein said step of generating a capacitance table corresponding to said effective contact/via width table includes:

inputting said effective contact/via width table into a field solver; and

inputting a process characterization file into said field solver, specifying process and technology parameters.

9. A method of extracting a parasitic capacitance of one or more contact/via in an integrated circuit layout comprising the steps of:

reading a technology file into an extraction system; and

reading a circuit layout into said extraction system;

wherein said technology file includes an capacitance table;

wherein the contact/via capacitance in said capacitance table is derived from an effective contact/via area table; and

wherein each element of said effective contact/via area table is calibrated to have a parasitic capacitance value matching with that of an actual contact/via configuration in an IC.

10. The method of claim 9, wherein each said element of said effective contact/via area table corresponds to a contact/via configuration having a polygon-shaped contact/via.

11. The method of claim 10, wherein each said element in said effective contact/via area table is represented in term of the width of a square-shaped contact/via.

12. The method of claim 9, wherein said effective contact/via area table includes an effective via area table corresponding to vias between two different interconnect layers in an IC.

13. The method of claim 9, wherein said technology file further includes capacitance and resistance of primitives other than contact and via.

14. The method of claim 9, wherein said technology file further includes process and technology parameters.

15. A method of conducting testing and simulation on an integrated circuit layout comprising the steps of:

creating a technology file;

processing the geometry of an integrated circuit layout; and

extracting parasitic capacitance by pattern-matching a contact/via configuration in said technology file from a pattern in said integrated circuit layout;

wherein said technology file includes an capacitance table;

wherein the contact/via capacitance in said capacitance table is derived from an effective contact/via area table; and

wherein each element of said effective contact/via area table is calibrated to have a parasitic capacitance value matching with that of an actual contact/via configuration in an IC.

16. The method of claim 15, wherein said step of creating in a technology file includes:

providing a plurality of contact/via capacitance test structures, having substantially similar dimensions and different contact/via configurations;

measuring parasitic contact/via capacitance on said plurality of test structures;

creating an effective contact/via width table, wherein each element of said table corresponds to a polygon-shaped contact/via and has a calculated parasitic capacitance matching to that of one of said plurality of test structures; and

generating a capacitance table corresponding to said effective contact/via width table.

17. The method of claim 16, wherein said step of creating said effective contact/via width table includes:

providing a measured value of contact/via parasitic capacitance;

preparing a process characterization file, said process characterization file including a trial value of a contact/via area;

calculating contact/via parasitic capacitance value by making use of a field solver with said process characterization file; and

comparing the calculated capacitance/via value with the measured contact/via parasitic capacitance value to determine an effective contact/via width.

18. The method of claim 17, wherein each element of said effective contact/via area table is calibrated to have a parasitic capacitance value matching with that of an actual contact/via configuration in an IC.

19. The method of claim 15, further comprises a step of extracting parasitic capacitance by interpolating and extrapolating capacitance values in said capacitance table of said technology file.

20. The method of claim 15 further comprises a step for outputting a parasitic extraction result in a netlist of RC values.