METHOD AND APPARATUS FOR PERFORMING RELATED TASKS ON MULTI-CORE PROCESSOR

• US 20090007117A1
• Filed: 12/31/2007
• Published: 01/01/2009
• Est. Priority Date: 06/26/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: CHO, Seung-mo
• Granted Patent: US 8,661,440 B2
• Time in Patent Office: Days
• US Class Current: 718/100
• CPC Class Codes: G06F 2209/5012 Processor sets
• CPC Class Codes: G06F 9/5027 the resource being a machine, e.g. CPUs, Servers, Terminals
• CPC Class Codes: G06F 9/5033 considering data affinity
• CPC Class Codes: G06F 9/5038 considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration scheduling strategies G06F9/4881 and subgroups

Abstract

A method and apparatus for performing related tasks in a multi-core processor are provided. The method of performing at least one related task on the multi-core processor including a plurality of cores, includes: determining whether data and address information which are required for performing the at least one related task are loaded in the cores of the multi-core processor; and controlling the multi-core processor based on a result of the determining so that the cores concurrently start to perform the at least one related task.

Claims

1. A method of performing at least one related task on a multi-core processor including a plurality of cores, the method comprising:

determining whether data and address information which are required for performing the at least one related task are loaded in the cores of the multi-core processor; and

controlling the multi-core processor based on a result of the determining, so that the cores concurrently start to perform the at least one related task.

2. The method of claim 1, wherein the address information is mapping information between an effect address (EA) for indicating an indirect address of a storage space in the multi-core processor and an real address (RA) for indicating a real address of the storage space which corresponds to the EA.

3. The method of claim 2, further comprising controlling the multi-core processor so that the mapping information is not changed while performing the at least one related task.

4. The method of claim 1, wherein the data and the address information which are required to perform the related tasks are loaded in at least one of memories and registers in the multi-core processor.

5. A method of performing at least one related task on a multi-core processor including a plurality of cores, the method comprising:

generating an application program interface (API) including information needed for performing the at least one related task; and

performing the at least one related task based on the generated API.

6. The method of claim 5, wherein the API includes a number of related tasks that are to be performed through the API and address information needed for performing the related tasks.

7. The method of claim 6, wherein the address information represents effect addresses (EAs) for indicating indirect addresses of storage spaces of the plurality of cores in which the related tasks are performed.

8. An apparatus for performing at least one related task on a multi-core processor including a plurality of cores, the apparatus comprising:

a determiner which determines whether data and address information which are required for performing the at least one related task are loaded in the plurality of cores of the multi-core processor; and

a controller which controls the multi-core processor based on a determination from the determiner result so that the cores concurrently start to perform the at least one related task.

9. The apparatus of claim 8, wherein the address information is mapping information between an effect address (EA) for indicating an indirect address of a storage space in the multi-core processor and a real address (RA) for indicating a real address of the storage space that corresponds to the EA.

10. The apparatus of claim 9, wherein the controller further controls the multi-core processor so that the mapping information is not changed while performing the at least one related task.

11. The apparatus of claim 8, wherein the data and the address information which are required to perform the at least one related task are loaded in at least one of a plurality of memories and registers in the multi-core processor.

12. An apparatus for performing at least one related task on a multi-core processor including a plurality of cores, the apparatus comprising:

an application program interface (API) generator which generates an API including information needed for performing the at least one related task; and

a task executor which performs the at least one related task based on the generated API.

13. The apparatus of claim 12, wherein the API includes a number of related tasks that are to be performed through the API and address information needed for performing the related tasks.

14. The apparatus of claim 13, wherein the address information represents effect addresses (EAs) for indicating indirect addresses of storage spaces of the plurality of cores in which the related tasks are performed.

15. A computer-readable recording medium having recorded thereon a method of performing at least one related task on a multi-core processor including a plurality of cores, the method comprising:

determining whether data and address information which are required for performing the at least one related task are loaded in the cores of the multi-core processor; and

controlling the multi-core processor based on a result of the determining, so that the cores concurrently start to perform the at least one related task.