Method And Apparatus To Enable Runtime Processor Migration With Operating System Assistance

• US 20090007121A1
• Filed: 06/30/2007
• Published: 01/01/2009
• Est. Priority Date: 06/30/2007
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Kumar, Mohan J., Yamada, Koichi, Vargas, Jose A., Covelli, Douglas E.
• Granted Patent: US 8,296,768 B2
• Time in Patent Office: Days
• US Class Current: 718/102
• CPC Class Codes: G06F 11/2028 eliminating a faulty processor or activating a spare
• CPC Class Codes: G06F 11/203 using migration
• CPC Class Codes: G06F 11/2051 in regular structures

Abstract

In a method for switching to a spare processor during runtime, a processing system determines that execution should be migrated off of an active processor. An operating system (OS) scheduler and at least one device are then paused, and the active processor is put into an idle state. State data from writable and substantial non-writable stores in the active processor is loaded into the spare processor. Interrupt routing table logic for the processing system is dynamically reprogrammed to direct external interrupts to the spare processor. The active processor may then be off-lined, and the device and OS scheduler may be unpaused or resumed. Threads may then be dispatched to the spare processor for execution. Other embodiments are described and claimed.

Claims

1. A method for switching to a spare processor during runtime, the method comprising:

determining that execution should be migrated off of an active processor in a processing system;

after determining that execution should be migrated off of the active processor, pausing an operating system (OS) scheduler in the processing system, pausing at least one device in the processing system, and putting the active processor into an idle state;

saving state data from writable and substantial non-writable stores in the active processor, to a store outside of the active processor,

starting a spare processor in the processing system;

loading the state data saved from the writeable store of the active processor to the spare processor;

loading the state data saved from the substantially non-writeable store of active processor to the spare processor;

reprogramming interrupt routing table logic for the processing system to direct external interrupts to the spare processor;

off-lining the active processor;

resuming the device; and

resuming the OS scheduler.

2. A method according to claim 1, wherein the operation of determining that execution should be migrated off of the active processor is performed by system firmware in the processing system.

3. A method according to claim 2, further comprising:

sending a pause request from the system firmware to the OS in response to determining that execution should be migrated off of the active processor.

4. A method according to claim 3, further comprising:

receiving a resume request from the system firmware at the OS; and

resuming the device in response to the receiving the resume request from the system firmware.

5. A method according to claim 3, further comprising:

putting all active processors in the processing system into an idle state, and pausing all devices in the processing system, before loading the state data from the substantially non-writeable store of active processor into the spare processor.

6. A method according to claim 1, wherein the operation of saving state data from writable and substantially non-writable stores in the active processor is performed after the active processor has entered the idle state.

7. A method according to claim 1, wherein the operation of reprogramming interrupt routing table logic for the processing system comprises:

reprogramming interrupt routing table logic in a chipset of the processing system; and

reprogramming interrupt routing table logic in an uncore of the spare processor.

8. A method according to claim 1, further comprising:

after resuming the OS scheduler, dispatching threads to the spare processor for execution.

9. A processing system that can switch to a spare processor during runtime, the processing system comprising:

a first processor to serve as an active processor operable to execute an operating system (OS);

a second processor to serve as a spare processor;

at least one device;

data storage;

one or more communication pathways in communication with the first processor, the second processor, the device, and the data storage;

control logic stored at least partial in the data storage, the control logic operable to perform operations comprising;

determining that execution should be migrated off of the active processor;

after determining that execution should be migrated off of the active processor, pausing a scheduler in the OS, pausing the device, and putting the active processor into an idle state;

saving state data from writable and substantial non-writable stores in the active processor, to a store outside of the active processor;

starting the spare processor,

loading the state data saved from the writeable store of the active processor to the spare processor;

loading the state data saved from the substantially non-writeable store of active processor to the spare processor;

reprogramming interrupt routing table logic for the processing system to direct external interrupts to the spare processor;

off-lining the active processor;

unpausing the device; and

unpausing the OS scheduler.

10. A processing system according to claim 9, further comprising:

the OS scheduler operable to dispatch threads to the spare processor for execution after the OS scheduler has been resumed.

11. A processing system according to claim 9, wherein at least a portion of the control logic comprises system firmware.

12. A processing system according to claim 9, further comprising the control logic operable to perform operations comprising:

sending a pause request to the OS in response to determining that execution should be migrated off of the active processor.

13. A processing system according to claim 9, further comprising the control logic operable to perform operations comprising:

saving the state data after the active processor has entered the idle state.

14. A processing system according to claim 9, further comprising the control logic operable to perform operations comprising:

putting all active processors in the processing system into an idle state, and pausing all devices in the processing system, before loading the state data from the substantially non-writeable store of active processor into the spare processor.

15. A processing system according to claim 9, further comprising:

a chipset in communication with at least one of the communication pathways, the chipset to contain interrupt routing table logic; and

an uncore in the spare processor, the uncore to contain interrupt routing table logic;

the control logic to reprogram interrupt routing table logic for the processing system to direct external interrupts to the spare processor by reprogramming the interrupt routing table logic in the chipset and the interrupt routing table logic in the uncore of the spare processor.

16. An apparatus, comprising:

a machine-accessible medium; and

instructions in the machine-accessible medium, wherein the instructions, when executed by a processing system having an active processor and a spare processor, cause the processing system to perform operations comprising;

determining that execution should be migrated off of the active processor;

after determining that execution should be migrated off of the active processor, pausing an operating system (OS) scheduler in the processing system, pausing at least one device in the processing system, and putting the active processor into an idle state;

saving state data from writable and substantially non-writable stores in the active processor, to a store outside of the active processor;

starting the spare processor;

loading the state data saved from the writeable store of the active processor to the spare processor;

loading the state data saved from the substantially non-writeable store of active processor to the spare processor;

reprogramming interrupt routing table logic for the processing system to direct external interrupts to the spare processor;

off-lining the active processor;

resuming the device;

resuming the OS scheduler; and

dispatching threads to the spare processor for execution.

17. An apparatus according to claim 16, wherein at least a portion of the instructions comprises system firmware.

18. An apparatus according to claim 16, wherein the instructions send a pause request to the OS in response to determining that execution should be migrated off of the active processor.

19. An apparatus according to claim 16, wherein the instructions cause the processing system to save the state data after the active processor has entered the idle state.

20. An apparatus according to claim 16, wherein the instructions cause the processing system to reprogram interrupt routing table logic for the processing system to direct external interrupts to the spare processor by (a) reprogramming interrupt routing table logic in a chipset of the processing system and (b) reprogramming interrupt routing table logic in an uncore of the spare processor.