NANOWIRE TUNNELING TRANSISTOR

• US 20090008631A1
• Filed: 01/24/2007
• Published: 01/08/2009
• Est. Priority Date: 01/25/2006
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Hurkx, Godefridus Andrianus Maria, Agarwal, Prabhat
• Granted Patent: US 7,791,108 B2
• Time in Patent Office: Days
• US Class Current: 257/25
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/068 comprising a junction
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: Y10S 977/75 Single-walled
• CPC Class Codes: Y10S 977/813 Of specified inorganic semiconductor composition, e.g. periodic table group IV-VI compositions
• CPC Class Codes: Y10S 977/938 Field effect transistors, FETS, with nanowire- or nanotube-channel region

Abstract

A transistor comprises a nanowire (22, 22′) having a source (24) and a drain (29) separated by an intrinsic or lowly doped region (26, 28). A potential barrier is formed at the interface of the intrinsic or lowly doped region (26, 28) and one of the source (24) and the drain (29). A gate electrode (32) is provided in the vicinity of the potential barrier such that the height of the potential barrier can be modulated by applying an appropriate voltage to the gate electrode (32).

Claims

1. Transistor comprising a nanowire having a source and a drain separated by an intrinsic or lowly doped region, wherein a potential barrier is formed at the interface of the intrinsic or lowly doped region and one of the source and the drain, wherein a gate electrode is provided in the vicinity of the potential barrier such that the effective height and/or width of the potential barrier can be modulated by applying an appropriate voltage to the gate electrode.

2. Transistor according to claim 1, wherein a barrier region is located inside the intrinsic or lowly doped region between the source and the drain.

3. Transistor according to claim 1 wherein the barrier is a highly doped semiconductor material.

4. Transistor according to claim 3, wherein the semiconductor material forming the barrier region is indium arsenide while the adjacent intrinsic or lowly doped regions are made of silicon or gallium arsenide.

5. Transistor according to claim 1, wherein the barrier is made from a metal.

6. Transistor according to claim 1, wherein the nanowire is grown on a semiconductor substrate.

7. Transistor according to claim 1, wherein the nanowire has highly doped end portions forming the source and the drain of the transistor.

8. Transistor according to claim 5, wherein the outer surface of the nanowire is covered by an insulating layer.

9. Transistor according to claim 8 wherein on the surface of the insulating layer a metal layer is deposited forming a gate electrode.

10. Transistor according to claim 8, wherein the insulating layer is a dielectric layer or a wide band gap semiconductor forming a Schottky barrier to the gate electrode.

11. Transistor according to claim 10, wherein the wide band gap semiconductor forming the Schottky barrier to the gate electrode contains a delta-doped layer.