Oxide semiconductor, thin film transistor including the same and method of manufacturing a thin film transistor

• US 20090008638A1
• Filed: 04/03/2008
• Published: 01/08/2009
• Est. Priority Date: 07/04/2007
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Song, I-hun, Lee, Eun-ha, Park, Young-soo, Kang, Dong-hun, Kim, Chang-jung, Lee, Jae-cheol
• Application Number:
  US12/078,706
• Publication Number:
  US 20090008638A1
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

Example embodiments relate to an oxide semiconductor including zinc oxide (ZnO), a thin film transistor including a channel formed of the oxide semiconductor and a method of manufacturing the thin film transistor. The oxide semiconductor may include a Ga_xIn_yZn_z oxide and at least one material selected from the group consisting of a 4A group element, a 4A group oxide, a rare earth element and combinations thereof.

Claims

1. An oxide semiconductor, comprising:

a Ga_xIn_yZn_z oxide; and

at least one material selected from the group consisting of a 4A group element, a 4A group oxide, a rare earth element and combinations thereof.

2. The oxide semiconductor of claim 1, wherein the Ga_xIn_yZn_z oxide is a Ga_xIn_yZn_z oxide compound.

3. The oxide semiconductor of claim 1, wherein the Ga_xIn_yZn_z oxide includes the at least one material.

4. The oxide semiconductor of claim 3, wherein an amount of the at least one material is in a range of 0.01 at % to 10.00 at %.

5. The oxide semiconductor of claim 1, wherein the 4A group element is at least one selected from the group consisting of titanium (Ti), zirconium (Zr), hafnium (Hf) and combinations thereof.

6. The oxide semiconductor of claim 5, wherein x, y and z are each independently an integer ranging from 0 to 1, and

the Ga_xIn_yZn_z oxide is at least one selected from the group consisting of TiInZn oxide, TiGaInZn oxide and combinations thereof.

7. The oxide semiconductor of claim 1, comprising:

a first oxide layer including the Ga_xIn_yZn_z oxide; and

a material layer on the first oxide layer, wherein the material layer includes the at least one material.

8. The oxide semiconductor of claim 7, wherein the material layer has a thickness of 5 nm to 20 nm.

9. The oxide semiconductor of claim 7, further comprising a second oxide layer on the material layer, wherein the second oxide layer includes the Ga_xIn_yZn_z oxide.

10. The oxide semiconductor of claim 1, wherein the oxide semiconductor has a poly-crystalline structure or nano-crystalline structure.

11. The oxide semiconductor of claim 1, wherein the oxide semiconductor has a poly-crystalline structure or a mixed-phase of a nano-crystalline structure and an amorphous structure.

12. The oxide semiconductor of claim 1, wherein, x, y, and z represent an atomic ratio, and at least one of the following equations x+y+z=1, x+y=1, x+z=1, y+z=1 and z=1 is satisfied.

13. A thin film transistor, comprising:

a gate;

a channel corresponding to the gate, wherein the channel includes the oxide semiconductor according to claim 1;

a gate insulator between the gate and the channel; and

a source and a drain each contacting a side surface of the channel.

14. The thin film transistor of claim 13, wherein the Ga_xIn_yZn_z oxide is a Ga_xIn_yZn_z oxide compound.

15. The thin film transistor of claim 13, wherein the Ga_xIn_yZn_z oxide includes the at least one material.

16. The thin film transistor of claim 15, wherein an amount of the at least one material is in a range of 0.01 at % to 10.00 at %.

17. The thin film transistor of claim 13, wherein the 4A group element is at least one selected from the group consisting of titanium (Ti), zirconium (Zr), hafnium (Hf) and combinations thereof.

18. The thin film transistor of claim 17, wherein x, y and z are each independently an integer ranging from 0 to 1, and

the Ga_xIn_yZn_z oxide is at least one selected from the group consisting of TiInZn oxide, TiGaInZn oxide and combinations thereof.

19. The thin film transistor of claim 13, wherein the channel includes:

a first oxide layer including the Ga_xIn_yZn_z oxide; and

a material layer on the first oxide layer, wherein the material layer includes the at least one material.

20. The thin film transistor of claim 19, wherein the material layer has a thickness of 5 nm to 20 nm.

21. The thin film transistor of claim 19, further comprising a second oxide layer on the material layer, wherein the second oxide layer includes the Ga_xIn_yZn_z oxide.

22. The thin film transistor of claim 13, wherein the oxide semiconductor has a poly-crystalline structure or nano-crystalline structure.

23. The thin film transistor of claim 13, wherein the oxide semiconductor has a poly-crystalline structure or a mixed-phase of a nano-crystalline structure and an amorphous structure.

24. The thin film transistor of claim 13, wherein, x, y, and z represent an atomic ratio, and at least one of the following equations x+y+z=1, x+y=1, x+z=1, y+z=1 and z=1 is satisfied.

25. A method of manufacturing a thin film transistor, comprising:

forming a gate and a gate insulating layer on the gate;

forming a channel on the gate insulating layer corresponding to the gate, wherein the channel includes a Ga_xIn_yZn_z oxide and at least one material selected from the group consisting of a 4A group element, a 4A group oxide, a rare earth element and combinations thereof; and

forming a source and a drain each contacting a side portion of the channel.

26. The method of claim 25, wherein the at least one material is formed in the Ga_xIn_yZn_z oxide.

27. The method of claim 26, wherein the channel is formed by doping the Ga_xIn_yZn_z oxide using at least one method selected from the group consisting of sputtering, CVD, ALD, laser assisted deposition, ion implantation and ion shower.

28. The method of claim 25, wherein the channel is formed by depositing and diffusing the at least one material in the Ga_xIn_yZn_z oxide using a thermal treatment.

29. The method of claim 28, wherein the thermal treatment is performed at a temperature of 100°

C. to 450°

C. using a furnace, rapid thermal annealing laser or hot plate.

30. The method of claim 25, comprising:

forming a first oxide layer including the Ga_xIn_yZn_z oxide; and

forming a material layer including the at least one material.

31. The method of claim 30, wherein the material layer has a thickness of 5 nm to 20 nm.

32. The method of claim 30, further comprising forming a second oxide layer on the material layer, wherein the second oxide layer includes the Ga_xIn_yZn_z oxide.

33. The method of claim 25, wherein, x, y and z represent an atomic ratio, and at least one of the following equations x+y+z=1, x+y=1, x+z=1, y+z=1, and z=1 is satisfied.