Power Semiconductor Devices with Trenched Shielded Split Gate Transistor and Methods of Manufacture

• US 20090008709A1
• Filed: 12/21/2007
• Published: 01/08/2009
• Est. Priority Date: 05/20/2003
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Yedinak, Joseph A., Kraft, Nathan L.
• Granted Patent: US 8,013,391 B2
• Time in Patent Office: Days
• US Class Current: 257/331
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/30655 comprising alternated and repeated etching and passivation steps, e.g. Bosch process
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/4952 the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 : with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 : within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 : the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 : characterised by the surface lay-out
• CPC Class Codes: H01L 29/4933 : with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/495 : the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66348 : with a recessed gate
• CPC Class Codes: H01L 29/66734 : with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7396 : with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7802 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7804 : the other device being a pn-junction diode
• CPC Class Codes: H01L 29/7805 : in antiparallel, e.g. freewheel diode
• CPC Class Codes: H01L 29/7806 : the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7815 : with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell
• CPC Class Codes: H01L 29/7828 : without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/7831 : with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/13034 : Silicon Controlled Rectifier [SCR]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H02M 3/00 : Conversion of dc power input into dc power output
• CPC Class Codes: H02M 3/33592 : having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
• CPC Class Codes: H02M 7/48 : using discharge tubes with control electrode or semiconductor devices with control electrode
• CPC Class Codes: Y02B 70/10 : Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A semiconductor power device includes a drift region of a first conductivity type, a well region extending above the drift region and having a second conductivity type opposite the first conductivity type, active trenches extending through the well region and into the drift region where the active trenches define an active area. Inside each of the active trenches is formed a first conductive gate electrode disposed along and insulated from a first trench sidewall, a second conductive gate electrode disposed along and insulated from a second trench sidewall, and a conductive shield electrode disposed between the first and second conductive gate electrodes, wherein the shield electrode is insulated from and extends deeper inside the trench than the first and second conductive gate electrodes. The device also includes source regions having the first conductivity type formed inside the well region and adjacent the active trenches. Electrical contact to the conductive shield electrode can be made inside the active area. The device can also include a perimeter trench extending at least partially around the active trenches such that at least some of the active trenches are perpendicular to the perimeter trench, gate fingers extending from a perimeter gate poly runner located in said perimeter trench, and shield poly fingers extending from a perimeter shield poly runner located in the perimeter trench. The gate fingers are staggered with respect to the shield poly fingers.

Claims

1-235. -235. (canceled)

236. A semiconductor device comprising:

a drift region of a first conductivity type;

a well region extending above the drift region and having a second conductivity type opposite the first conductivity type;

a plurality of active trenches extending through the well region and into the drift region, the plurality of active trenches defining an active area, wherein inside each of the plurality of active trenches is formed;

a first conductive gate electrode disposed along and insulated from a first trench sidewall,

a second conductive gate electrode disposed along and insulated from a second trench sidewall, and

a conductive shield electrode disposed between the first and second conductive gate electrodes, wherein the shield electrode is insulated from and extends deeper inside the trench than the first and second conductive gate electrodes; and

source regions having the first conductivity type formed inside the well region and adjacent the plurality of active trenches,

wherein, electrical contact to the conductive shield electrode is made inside the active area.

237. The semiconductor device of claim 236 further comprising a perimeter trench extending at least partially around the plurality of active trenches such that at least some of the plurality of active trenches are perpendicular to the perimeter trench.

238. The semiconductor device of claim 237 wherein the perimeter trench does not connect to the plurality of active trenches.

239. The semiconductor device of claim 237 wherein the perimeter trench connects to the plurality of trenches.

240. The semiconductor device of claim 237 wherein the perimeter trench is substantially filled with a layer of conductive material that is insulated from the trench sidewalls.

241. The semiconductor device of claim 238 wherein a first distance between the perimeter trench and end of an active trench is smaller than a second distance between two active trenches.

242. The semiconductor device of claim 241 wherein the first distance is about half of the second distance.

243. The semiconductor device of claim 237 further comprising:

a plurality of gate fingers extending from a perimeter gate poly runner located in said perimeter trench; and

a plurality of shield poly fingers extending from a perimeter shield poly runner located in said perimeter trench.

244. The semiconductor device of claim 243 wherein said plurality of gate fingers are staggered with respect to said plurality of shield poly fingers.

245. The semiconductor device of claim 243 wherein said plurality of gate fingers are spaced apart from said shield poly fingers.

246. The semiconductor device of claim 243 wherein said plurality of gate fingers are all equally spaced apart from said shield poly fingers.

247. The semiconductor device of claim 236 further comprising a termination trench at the outer periphery of the plurality of active trenches, wherein the termination trench is substantially filled with conductive material that is insulated from trench sidewalls.

248. The semiconductor device of claim 247 wherein a mesa formed between the termination trench and an active trench adjacent the termination trench comprises a region having the second conductivity type.

249. The semiconductor device of claim 236 wherein contact to the well region is made via a body trench that is etched into a central portion of a mesa between adjacent active trenches.

250. The semiconductor device of claim 249 wherein the body trench extends deeper inside the well region than the source regions.

251. The semiconductor device of claim 249 wherein the body trench extends deeper than the well region.

252. The semiconductor device of claim 249 further comprising a region of high dopant concentration having the second conductivity type located at least under the body trench.

253. The semiconductor device of claim 236 wherein said first conductive gate electrode and said second conductive gate electrode extend deeper than the well region.

254. A semiconductor device comprising:

a plurality of active trenches defining an active area;

a perimeter trench extending at least partially around the plurality of active trenches such that at least some of the plurality of active trenches are perpendicular to the perimeter trench;

a plurality of gate fingers extending from a perimeter gate poly runner located in said perimeter trench; and

a plurality of shield poly fingers extending from a perimeter shield poly runner located in said perimeter trench;

wherein said plurality of gate fingers are staggered with respect to said plurality of shield poly fingers.

255. A method of manufacturing a semiconductor device comprising:

forming trenches in a substrate;

depositing a shield oxide layer that conforms to the trenches;

depositing a gate polysilicon layer into the trenches;

etching the gate polysilicon layer so that the gate polysilicon layer is recessed in the trench;

etching the shield oxide layer so that the shield oxide layer is recessed in the trench and lower than the gate polysilicon layer;

depositing a layer of gate oxide across the top of the substrate, sidewalls of the trenches and troughs inside the trenches leaving a recess;

depositing shield polysilicon in the recess;

etching the shield polysilicon layer so that the shield polysilicon layer is recessed in the trench and higher than the gate polysilicon layer;

forming a well region; and

forming a source region.

256. The method of claim 255 wherein forming a well region is performed with −

p-well implant.

257. The method of claim 255 wherein forming a source region is performed with an n+ source implant.

258. The method of claim 255 further comprising depositing a layer of BPSG.

259. The method of claim 255 further comprising performing a contact etch and p+ heavy body implant

260. The method of claim 255 further comprising metallizing the surfaces to form a source contact region and drain contact region.

261. The method of claim 255 further comprising leaving an exposed portion of the shield polysilicon layer that forms two troughs on its sides inside the trench.