Power Semiconductor Devices with Trenched Shielded Split Gate Transistor and Methods of Manufacture
8 Assignments
0 Petitions
Accused Products
Abstract
A semiconductor power device includes a drift region of a first conductivity type, a well region extending above the drift region and having a second conductivity type opposite the first conductivity type, active trenches extending through the well region and into the drift region where the active trenches define an active area. Inside each of the active trenches is formed a first conductive gate electrode disposed along and insulated from a first trench sidewall, a second conductive gate electrode disposed along and insulated from a second trench sidewall, and a conductive shield electrode disposed between the first and second conductive gate electrodes, wherein the shield electrode is insulated from and extends deeper inside the trench than the first and second conductive gate electrodes. The device also includes source regions having the first conductivity type formed inside the well region and adjacent the active trenches. Electrical contact to the conductive shield electrode can be made inside the active area. The device can also include a perimeter trench extending at least partially around the active trenches such that at least some of the active trenches are perpendicular to the perimeter trench, gate fingers extending from a perimeter gate poly runner located in said perimeter trench, and shield poly fingers extending from a perimeter shield poly runner located in the perimeter trench. The gate fingers are staggered with respect to the shield poly fingers.
-
Citations
261 Claims
-
1-235. -235. (canceled)
-
236. A semiconductor device comprising:
-
a drift region of a first conductivity type; a well region extending above the drift region and having a second conductivity type opposite the first conductivity type; a plurality of active trenches extending through the well region and into the drift region, the plurality of active trenches defining an active area, wherein inside each of the plurality of active trenches is formed; a first conductive gate electrode disposed along and insulated from a first trench sidewall, a second conductive gate electrode disposed along and insulated from a second trench sidewall, and a conductive shield electrode disposed between the first and second conductive gate electrodes, wherein the shield electrode is insulated from and extends deeper inside the trench than the first and second conductive gate electrodes; and source regions having the first conductivity type formed inside the well region and adjacent the plurality of active trenches, wherein, electrical contact to the conductive shield electrode is made inside the active area. - View Dependent Claims (237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253)
-
-
254. A semiconductor device comprising:
-
a plurality of active trenches defining an active area; a perimeter trench extending at least partially around the plurality of active trenches such that at least some of the plurality of active trenches are perpendicular to the perimeter trench; a plurality of gate fingers extending from a perimeter gate poly runner located in said perimeter trench; and a plurality of shield poly fingers extending from a perimeter shield poly runner located in said perimeter trench; wherein said plurality of gate fingers are staggered with respect to said plurality of shield poly fingers.
-
-
255. A method of manufacturing a semiconductor device comprising:
-
forming trenches in a substrate; depositing a shield oxide layer that conforms to the trenches; depositing a gate polysilicon layer into the trenches; etching the gate polysilicon layer so that the gate polysilicon layer is recessed in the trench; etching the shield oxide layer so that the shield oxide layer is recessed in the trench and lower than the gate polysilicon layer; depositing a layer of gate oxide across the top of the substrate, sidewalls of the trenches and troughs inside the trenches leaving a recess; depositing shield polysilicon in the recess; etching the shield polysilicon layer so that the shield polysilicon layer is recessed in the trench and higher than the gate polysilicon layer; forming a well region; and forming a source region. - View Dependent Claims (256, 257, 258, 259, 260, 261)
-
Specification