Fully Isolated High-Voltage MOS Device

• US 20090008711A1
• Filed: 07/03/2007
• Published: 01/08/2009
• Est. Priority Date: 07/03/2007
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wu, Kuo-Ming, Wei, Chi-San, Lin, Yi-Chun
• Granted Patent: US 7,843,002 B2
• Time in Patent Office: Days
• US Class Current: 257/339
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A semiconductor structure includes a semiconductor substrate; an n-type tub extending from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the n-type tub comprises a bottom buried in the semiconductor substrate; a p-type buried layer (PBL) on a bottom of the tub, wherein the p-type buried layer is buried in the semiconductor substrate; and a high-voltage n-type metal-oxide-semiconductor (HVNMOS) device over the PBL and within a region encircled by sides of the n-type tub.

Claims

1. A semiconductor structure comprising:

a semiconductor substrate;

an n-type tub extending from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the n-type tub comprises a bottom buried in the semiconductor substrate;

a p-type buried layer (PBL) on a bottom of the tub, wherein the p-type buried layer is buried in the semiconductor substrate; and

a high-voltage n-type metal-oxide-semiconductor (HVNMOS) device over the PBL and within a region encircled by sides of the n-type tub.

2. The semiconductor structure of claim 1, wherein the n-type tub has four sides each extending from the bottom of the tub upward substantially to the top surface of the semiconductor substrate, and wherein each of the sides comprises a first portion, and a second portion on the first portion, and wherein the first and the second portions have substantially discontinuous impurity concentrations.

3. The semiconductor structure of claim 2, wherein the first portions of the sides have a substantially higher impurity concentration that the bottom of the n-type tub.

4. The semiconductor structure of claim 2, wherein the first and the second portions have different widths.

5. The semiconductor structure of claim 1, wherein the n-type tub comprises four sides each extending from the bottom of the tub upward to the top surface of the semiconductor substrate;

and wherein the sides and the bottom of the n-type tub have substantially different impurity concentrations.

6. The semiconductor structure of claim 1 further comprising:

a high-voltage p-well (HVPW) region over the PBL;

a high-voltage n-well (HVNW) region over the PBL;

a gate dielectric extending from over the HVPW region to over the HVNW region;

a gate electrode on the gate dielectric;

a source region in the HVPW region and adjacent the gate electrode; and

a drain region in the HVNW region and adjacent the gate electrode.

7. The semiconductor structure of claim 6, wherein the n-type tub comprises four sides having a same impurity concentration as the HVNW region.

8. The semiconductor structure of claim 1, wherein the PBL fully covers the bottom of the n-type tub.

9. A semiconductor structure comprising:

a semiconductor substrate;

a first high-voltage n-well (HVNW) region in the semiconductor substrate;

a second HVNW region in the semiconductor substrate, wherein the first and the second HVNW regions are parallel;

a third HVNW region between the first and the second HVNW regions;

a first high-voltage p-well (HVPW) region between the first and the second HVNW regions;

a first and a second n-type isolation (N-ISO) region underlying and adjoining the first and the second HVNW regions, respectively;

an n-type buried layer (NBL) connecting the first and the second N-ISO regions; and

a p-type buried layer (PBL) on the NBL.

10. The semiconductor structure of claim 9, wherein the PBL extends horizontally beyond a region between the first and the second HVNW regions.

11. The semiconductor structure of claim 9, wherein the first and the second N-ISO regions have substantially different impurity concentrations from the first and the second HVNW regions.

12. The semiconductor structure of claim 9, wherein the first and the second N-ISO regions have substantially different impurity concentrations from the NBL region.

13. The semiconductor structure of claim 12, wherein the first and the second N-ISO regions have a substantially higher impurity concentration than the NBL region.

14. The semiconductor structure of claim 12, wherein the first and the second N-ISO regions have different widths from the first and the second HVNW regions.

15. The semiconductor structure of claim 12 further comprising;

a fourth and a fifth HVNW region; and

a third and a fourth N-ISO region underlying and adjoining the fourth and the fifth HVNW regions, respectively, wherein the first, the second, the fourth and the fifth HVNW regions form a ring, and wherein the first, the second, the third and the fourth N-ISO regions form a ring.

16. A semiconductor structure comprising:

a semiconductor substrate of a p-type conductivity;

an epitaxial layer on the semiconductor substrate;

an n-type buried layer (NBL) extending from the semiconductor substrate into the epitaxial layer;

a p-type buried layer (PBL) on the NBL;

an n-type isolation region (N-ISO) ring extending from the semiconductor substrate into the epitaxial layer, wherein the N-ISO ring encircles and adjoins the NBL and at least a portion of the PBL;

a high-voltage n-well (HVNW) ring on and adjoining the N-ISO ring; and

a high-voltage n-type metal-oxide-semiconductor (HVNMOS) device over the PBL, wherein a portion of the HVNMOS device in the epitaxial layer is encircled by the HVNW ring.

17. The semiconductor structure of claim 16, wherein the HVNMOS device comprises a source in a high-voltage p-well (HVPW) region, a drain in a high-voltage n-well (HVNW) region, and wherein the HVPW region and the HVNW region each have a bottom interface adjoining the PBL.

18. The semiconductor structure of claim 16, wherein the N-ISO ring has a higher impurity concentration than the NBL.

19. The semiconductor structure of claim 16, wherein the N-ISO ring has a different impurity concentration from the HVNW ring.

20. The semiconductor structure of claim 16 further comprising a p-type region between the NBL and the semiconductor substrate, wherein the p-type region has a higher p-type impurity concentration than the semiconductor substrate.