STRESS ENHANCED CMOS CIRCUITS

• US 20090008718A1
• Filed: 08/27/2008
• Published: 01/08/2009
• Est. Priority Date: 09/18/2006
• Status: Active Grant

• Current Assignee: Innovative Foundry Technologies LLC
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: LUNING, Scott D., van MEER, Johannes, PEI, Gen
• Granted Patent: US 9,373,548 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A CMOS circuit is provided that includes a PMOS transistor, an NMOS transistor adjacent the PMOS transistor in a channel width direction, a compressive stress liner overlying the PMOS transistor, and a tensile stress liner overlying the NMOS transistor. A portion of the compressive stress liner and a portion of the tensile stress liner are in a stacked configuration, and an overlap region of the compressive stress liner and the tensile stress liner is sufficient to result in an enhanced transverse stress in the compressive stress liner or the tensile stress liner.

Claims

1. A CMOS circuit comprising:

a PMOS transistor;

an NMOS transistor adjacent the PMOS transistor in a channel width direction;

a compressive stress liner overlying the PMOS transistor; and

a tensile stress liner overlying the NMOS transistor,

wherein a portion of the compressive stress liner and a portion of the tensile stress liner are in a stacked configuration and an overlap region of the compressive stress liner and the tensile stress liner is sufficient to result in an enhanced transverse stress in the compressive stress liner or the tensile stress liner.

2. The CMOS circuit of claim 1, wherein the portion of the compressive stress liner is an edge portion of the compressive stress liner and wherein the portion of the tensile stress liner overlies the edge portion of the compressive stress liner

3. The CMOS circuit of claim 1, wherein the portion of the tensile stress liner is an edge portion of the tensile stress liner and wherein the portion of the compressive stress liner overlies the edge portion of the tensile stress liner.

4. The CMOS circuit of claim 1, further comprising:

an isolation region that separates the NMOS transistor from the PMOS transistor, wherein the compressive stress liner overlies a first portion of the isolation region and wherein the tensile stress liner overlies a second portion of the isolation region

5. The CMOS circuit of claim 1, further comprising:

a second NMOS transistor adjacent the PMOS transistor in a channel length direction; and

a dummy region positioned between the PMOS transistor and the second NMOS transistor.

6. A CMOS circuit comprising:

a PMOS transistor;

an isolation region;

an NMOS transistor adjacent the PMOS transistor in a channel width direction and separated from the PMOS transistor by the isolation region;

a compressive stress liner overlying the PMOS transistor and a first portion of the isolation region; and

a tensile stress liner overlying the NMOS transistor, a second portion of the isolation region, and an edge portion of the compressive stress liner.

7. The CMOS circuit of claim 6, wherein the tensile stress liner overlies a portion but not the entirety of the PMOS transistor.

8. The CMOS circuit of claim 6, wherein the compressive stress liner comprises a first silicon nitride layer, and the tensile stress liner comprises a second silicon nitride layer.

9. The CMOS circuit of claim 6, further comprising:

a second NMOS transistor adjacent the PMOS transistor in a channel length direction; and

a dummy region positioned between the PMOS transistor and the second NMOS transistor.

10. The CMOS circuit of claim 9, wherein the PMOS transistor is separated from the second NMOS transistor by the isolation region therebetween.

11. The CMOS circuit of claim 10, wherein the dummy region overlies the isolation region between the PMOS transistor and the second NMOS transistor.

12. The CMOS circuit of claim 9, wherein the compressive stress liner extends over a first portion of the dummy region.

13. The CMOS circuit of claim 12, wherein the tensile stress liner extends over a second portion of the dummy region, wherein the first portion of the dummy region and the second portion of the dummy region are mutually exclusive.

14. The CMOS circuit of claim 9, wherein the dummy region comprises polycrystalline silicon.

15. A CMOS circuit comprising:

a PMOS transistor;

an isolation region;

an NMOS transistor adjacent the PMOS transistor in a channel width direction and separated from the PMOS transistor by the isolation region;

a second NMOS transistor adjacent the PMOS transistor in a channel length direction;

a dummy region positioned between the PMOS transistor and the second NMOS transistor;

a compressive stress liner overlying the PMOS transistor, a first portion of the isolation region, and a first portion of the dummy region; and

a tensile stress liner overlying the NMOS transistor, a second portion of the isolation region, and a second portion of the dummy region, wherein the first portion of the dummy region and the second portion of the dummy region are mutually exclusive and wherein a portion of the compressive stress liner and a portion of the tensile stress liner are in a stacked configuration.

16. The CMOS circuit of claim 15, wherein the PMOS transistor is separated from the second NMOS transistor by the isolation region therebetween, and wherein the dummy region overlies the isolation region between the PMOS transistor and the second NMOS transistor.