SEMICONDUCTOR DEVICE

• US 20090010072A1
• Filed: 06/19/2008
• Published: 01/08/2009
• Est. Priority Date: 07/27/2001
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi ULSI Systems Company Limited (Hitachi, Ltd.), Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: TANAKA, Toshihiro, Katayama, Kozo, Matsuzaki, Nozomu, Hiraki, Mitsuru, Minami, Shinichi, Yamaki, Takashi, Fujito, Masamichi, Shinagawa, Yutaka, Tanikawa, Hiroyuki, Suzukawa, Kazufumi, Umemoto, Yukiko, Kamigaki, Yoshiaki
• Granted Patent: US 7,700,992 B2
• Time in Patent Office: Days
• US Class Current: 365/185.230
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H01L 21/28 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268 etching for patterning the electrodes H01L21/311, H01L21/3213; multistep manufacturing processes for data storage electrodes H01L29/4011
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/4234 Gate electrodes for transistors with charge trapping gate insulator
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/49 : comprising different types of peripheral transistor
• CPC Class Codes: H10B 69/00 : Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc<tm.

Claims

1-91. -91. (canceled)

92. An integrated microcomputer comprising:

a bus;

a central processing unit coupled to the bus; and

a non-volatile memory coupled to the bus and including;

a plurality of nonvolatile memory cells each having a first gate and a second gate;

a first circuit coupled to the first gates of ones of the plurality of nonvolatile memory cells;

a second circuit coupled to the second gates of ones of the plurality of nonvolatile memory cells; and

a voltage generation circuit which supplies a first voltage to the first circuit and supplies a second voltage to the second circuit,

wherein a gate withstand voltage of the first circuit is lower than that of the second circuit.

93. An integrated microcomputer according to claim 92,

wherein each of the plurality of nonvolatile memory cells has a charge storage region between the second gate thereof and a channel region.

94. An integrated microcomputer according to claim 92,

wherein the first circuit is arranged on a first side of the plurality of nonvolatile memory cells.

95. An integrated microcomputer according to claim 94,

wherein the second circuit is arranged on a second side, which is opposite side to the first side, of the plurality of nonvolatile memory cells.

96. An integrated microcomputer according to claim 92,

wherein the central processing unit has a MOS transistor, and

wherein a gate withstand voltage of the MOS transistor in the central processing unit is lower than that of the second circuit.

97. A microcomputer on a semiconductor chip, comprising:

a bus;

a central processing unit coupled to the bus and having a MOS transistor; and

a flash memory coupled to the bus and including;

a plurality of nonvolatile memory cells each having a first gate and a second gate;

a first driver coupled to the first gates of ones of the plurality of nonvolatile memory cells;

a second driver coupled to the second gates of ones of the plurality of nonvolatile memory cells; and

a voltage generator which supplies a first voltage to the first circuit and supplies a second voltage to the second circuit,

wherein a gate withstand voltage of the first driver and a gate withstand voltage of the MOS transistor in the central processing unit are lower than that of the second driver.

98. An integrated microcomputer according to claim 97,

wherein each of the plurality of nonvolatile memory cells has a charge storage region between the second gate thereof and a channel region.

99. An integrated microcomputer according to claim 97,

wherein the first driver is arranged on a first side of the plurality of nonvolatile memory cells.

100. An integrated microcomputer according to claim 99,

wherein the second driver is arranged on a second side, which is opposite side to the first side, of the plurality of nonvolatile memory cells.

101. An integrated data processor on a semiconductor chip, comprising:

a bus;

a central processing unit coupled to the bus and having a MOS transistor; and

a flash memory coupled to the bus and including;

a plurality of nonvolatile memory cells each having a first control gate and a second control gate;

a plurality of word lines, a plurality of bit lines, a plurality of control lines and a plurality of source lines coupled to the plurality of memory cells such that one word line, one bit line, one control line and one source line are coupled to one nonvolatile memory cell;

a first driver coupled to the first control gate of a corresponding nonvolatile memory cell via the corresponding word line;

a second driver coupled to the second control gate of the corresponding nonvolatile memory cell via the corresponding control line; and

a voltage generator which supplies a first voltage to the first driver and supplies a second voltage to the second driver, and

wherein a gate withstand voltage of the first driver is lower than that of the second driver.

102. An integrated data processor according to claim 101,

wherein the plurality of nonvolatile memory cells each has a charge storage region between the second control gate thereof and a channel region.

103. An integrated data processor according to claim 101,

wherein the central processing unit has a MOS transistor, and

wherein a gate withstand voltage of the MOS transistor in the central processing unit is lower than that of the second driver.

104. An integrated data processor according to claim 101,

wherein the first driver is arranged on a first side of the plurality of nonvolatile memory cells.

105. An integrated microcomputer according to claim 104,

wherein the second driver is arranged on a second side, which is opposite side to the first side, of the plurality of nonvolatile memory cells.