SIGNALING METHOD IN AN OFDM MULTIPLE ACCESS SYSTEM

• US 20090010351A1
• Filed: 07/10/2008
• Published: 01/08/2009
• Est. Priority Date: 09/13/2000
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Uppala, Sathyadev Venkata, Laroia, Rajiv, Li, Junyi
• Granted Patent: US 8,014,271 B2
• Time in Patent Office: Days
• US Class Current: 375/260
• CPC Class Codes: H04L 27/2602 Signal structure
• CPC Class Codes: H04L 27/26025 Numerology, i.e. varying one or more of symbol duration, subcarrier spacing, Fourier transform size, sampling rate or down-clocking allocating sub-channels of the transmission path H04L5/003
• CPC Class Codes: H04L 27/2614 Peak power aspects
• CPC Class Codes: H04L 27/2636 with FFT or DFT modulators, e.g. standard single-carrier frequency-division multiple access [SC-FDMA] transmitter or DFT spread orthogonal frequency division multiplexing [DFT-SOFDM]
• CPC Class Codes: H04L 5/0007 the frequencies being orthogonal, e.g. OFDM(A), DMT
• CPC Class Codes: H04L 5/023 Multiplexing of multicarrier modulation signals multicarrier modulation H04L27/2601

Abstract

A method for reducing the peak-to-average ratio in an OFDM communication signal is provided. The method includes defining a constellation having a plurality of symbols, defining a symbol duration for the OFDM communication signal, and defining a plurality of time instants in the symbol duration. A plurality of tones are allocated to a particular communication device, and a discrete signal is constructed in the time domain by mapping symbols from the constellation to the time instants. A continuous signal is generated by applying an interpolation function to the discrete signal such that the continuous signal only includes sinusoids having frequencies which are equal to the allocated tones.

Claims

1. A processing system configured to generate a signal to be transmitted over a wireless communication link comprising:

a first block configured to receive a plurality of digital samples and to generate a frequency domain response signal based upon the plurality of digital samples;

a second block coupled with the first block, the second block configured to receive the frequency domain response signal and to generate a time domain response signal based thereon; and

a cyclic prefix generator configured to receive the time domain response signal and to prepend a cyclic prefix to the time domain response signal.

2. The processing system of claim 1 wherein the first block comprises a discrete Fourier transform.

3. The processing system of claim 2 wherein the second block comprises an inverse discrete Fourier transform.

4. The processing system of claim 1 wherein the first block is configured to perform a discrete Fourier transform to generate the frequency domain response signal.

5. The processing system of claim 4 wherein the second block is configured to perform an inverse discrete Fourier transform to generate the time domain response signal.

6. The processing system of claim 1 wherein the frequency domain response signal comprises a plurality of values and the processing system further comprises a mapper configured to map the plurality of values to a plurality of array positions.

7. The processing system of claim 6 wherein the array position correspond to tones used for transmission.

8. The processing system of claim 6 wherein the mapper assigns a zero value to each array position that does correspond to a tone to be used for signal transmission.

9. The processing system of claim 6 wherein each value comprises a complex value.

10. The processing system of claim 1 further comprising a zero insertion circuit configured to receive the frequency domain response signal and to assign a zero value to each frequency which does not have a value in the frequency domain response signal.

11. The processing system of claim 1, wherein the first block and the second block comprise a digital signal processor.

12. The processing system of claim 1 wherein the time domain response signal comprises a plurality of sinusoids.

13. The processing system of claim 1 wherein at least some of the plurality of sinusoids have a zero magnitude.

14. The processing system of claim 1 wherein the second block comprises an inverse fast Fourier transform.

15. The processing system of claim 1 wherein the frequency domain response signal comprises a plurality of complex values.

16. The processing system of claim 15 wherein at least some of the plurality of complex values have a zero magnitude.

17. The processing system of claim 1 wherein the time domain response signal comprises a continuous signal.

18. A processing system configured to generate a signal to be transmitted over a wireless communication link comprising:

a first block configured to receive a plurality of digital samples and to generate a frequency domain response signal based upon the plurality of digital samples;

a second block coupled with the first block, the second block configured to receive the frequency domain response signal and to generate a time domain response signal based thereon; and

a cyclic prefix generator configured to receive the time domain response signal and to prepend a cyclic prefix to the time domain response signal.

19. The method of claim 18 wherein generating the frequency domain response signal comprises utilizing a discrete Fourier transform.

20. The method of claim 18 wherein generating the time domain response signal comprises utilizing an inverse discrete Fourier transform.

21. The method of claim 18 wherein the frequency domain response signal comprises a plurality of values and the method further comprises mapping the plurality of values to a plurality of array positions.

22. The method of claim 21 wherein the array position correspond to tones used for transmission.

23. The method of claim 21 wherein mapping comprises assigning a zero value to each array position that does correspond to a tone to be used for signal transmission.

24. The method of claim 21 wherein each value comprises a complex value.

25. The method of claim 18 further comprising assigning a zero value to each frequency which does not have a value in the frequency domain response signal.

26. The method of claim 18 wherein the time domain response signal comprises a plurality of sinusoids.

27. The method of claim 26 wherein at least some of the plurality of sinusoids have a zero magnitude.

28. The method of claim 18 wherein generating the time domain response signal comprises using an inverse fast Fourier transform.

29. The method of claim 18 wherein the frequency domain response signal comprises a plurality of complex values.

30. The method of claim 29 wherein at least some of the plurality of complex values have a zero magnitude.

31. The method of claim 18 wherein the time domain response signal comprises a continuous signal.

32. A processing system configured to generate a signal to be transmitted over a wireless communication link comprising:

a first block configured to receive a plurality of digital samples and to generate a frequency domain response signal based upon the plurality of digital samples;

means for mapping the frequency domain response signal to a plurality of tones;

a second block coupled with the means for mapping, the second block configured to receive the frequency domain response signal mapped to the plurality of tones and to generate a time domain response signal of the frequency domain response mapped to the plurality of tones; and

a cyclic prefix generator configured to receive the time domain response and to append a cyclic prefix to the time domain response signal.

33. The processing system of claim 32 wherein the first block comprises a discrete Fourier transform.

34. The processing system of claim 32 wherein the second block comprises an inverse discrete Fourier transform.

35. The processing system of claim 32 wherein the frequency domain response signal comprises a plurality of values and the means for mapping comprises means for mapping the plurality of values to a plurality of array positions.

36. The processing system of claim 35 wherein the array position correspond to tones used for transmission.

37. The processing system of claim 35 wherein the means for mapping comprises means for assigning a zero value to each array position that does correspond to a tone to be used for signal transmission.

38. The processing system of claim 35 wherein each value comprises a complex value.

39. The processing system of claim 35 wherein the means for mapping comprise means for assigning a zero value to each frequency which does not have a value in the frequency domain response signal.

40. The processing system of claim 35 wherein the time domain response signal comprises a plurality of sinusoids.

41. The processing system of claim 40 wherein at least some of the plurality of sinusoids have a zero magnitude.

42. The processing system of claim 35 wherein the second block comprises an inverse fast Fourier transform.

43. The processing system of claim 35 wherein the frequency domain response signal comprises a plurality of complex values.

44. The processing system of claim 43 wherein at least some of the plurality of complex values have a zero magnitude.

45. The processing system of claim 35 wherein the time domain response signal comprises a continuous signal.

46. A digital signal processor comprising:

a first block configured to generate a frequency domain response signal based upon a plurality of digital samples;

a second block configured to generate a time domain response signal of the frequency domain response signal; and

a cyclic prefix generator configured to receive the time domain response and to prepend a cyclic prefix to the time domain response signal.

47. The digital signal processor of claim 46 wherein the first block comprises a discrete Fourier transform and the second block comprises an inverse discrete Fourier transform.

48. The digital signal processor of claim 46 wherein the first block is configured to perform a discrete Fourier transform to generate the frequency domain response signal and the second block is configured to perform an inverse discrete Fourier transform to generate the time domain response signal.

49. The digital signal processor of claim 46 wherein the frequency domain response signal comprises a plurality of values and the digital signal processor further comprising a mapping block configured to map a plurality of values of the frequency domain response signal to a plurality array positions.

50. The digital signal processor of claim 46 wherein the frequency domain response signal comprises a plurality of values and the digital signal processor further comprising a mapping block configured to assign a zero value to each frequency which does not have a value in the frequency domain response signal.