COOLING OF SUBSTRATE USING INTERPOSER CHANNELS

• US 20090011546A1
• Filed: 09/18/2008
• Published: 01/08/2009
• Est. Priority Date: 09/02/2004
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: Lawrence S. Mok, Minhua Lu
• Inventors: Mok, Lawrence S., Lu, Minhua
• Granted Patent: US 7,856,711 B2
• Time in Patent Office: Days
• US Class Current: 438/122
• CPC Class Codes: F28D 15/0266 with separate evaporating and condensing chambers connected by at least one conduit; Loop-type heat pipes; with multiple or common evaporating or condensing chambers F28D15/043 takes precedence
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/427 Cooling by change of state, e.g. use of heat pipes by liquefied gas H01L23/445
• CPC Class Codes: H01L 23/433 Auxiliary members in containers characterised by their shape, e.g. pistons
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: Y10T 29/49126 Assembling bases
• CPC Class Codes: Y10T 29/49128 Assembling formed circuit to base
• CPC Class Codes: Y10T 29/4913 Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49165 by forming conductive walled aperture in base
• CPC Class Codes: Y10T 29/49204 Contact or terminal manufacturing

Abstract

A method of forming structure. A substrate and an interposer are provided. The substrate includes a heat source and N continuous substrate channels on a first side of the substrate (N≧2). N interposer channels are coupled to the N substrate channels so as to form M continuous loops (1≦M≦N). Each loop independently consists of K substrate channels and K interposer channels in an alternating sequence. For each loop, K is at least 1 and is subject to an upper limit consistent with a constraint of the M loops collectively consisting of the N interposer channels and the N substrate channels. Each loop is independently open ended or closed. The first side of the substrate is connected to the interposer. The interposer is adapted to be thermally coupled to a heat sink such that the interposer is interposed between the substrate and the heat sink.

Claims

1. A method of forming a structure, said method comprising:

providing a substrate, said substrate comprising N continuous substrate channels on a first side of the substrate, said substrate having a heat source therein, said N being at least 2;

providing an interposer, said interposer comprising N continuous interposer channels;

coupling the N interposer channels to the N substrate channels so as to form M continuous loops such that 1≦

M≦

N, each loop of the M loops independently consisting of K substrate channels of the N substrate channels and K interposer channels of the N interposer channels in an alternating sequence of substrate channels and interposer channels, for each loop of the M loops said K is at least 1 and is subject to an upper limit consistent with a constraint of having the M loops collectively consist of the N interposer channels and the N substrate channels, each loop of the M loops independently being open ended or closed, said first side of the substrate being connected to the interposer, said interposer adapted to be thermally coupled to a heat sink such that the interposer is interposed between the substrate and the heat sink.

2. The method of claim 1, wherein said M=N.

3. The method of claim 1, wherein said M=1 such that the M continuous loops consist of one continuous loop.

4. The method of claim 3, wherein the one continuous loop is open ended.

5. The method of claim 1, wherein 1<

M<

N.

6. The method of claim 5, wherein K>

1 in each loop of the M loops.

7. The method of claim 6, wherein each loop of the same loops has a same value of K.

8. The method of claim 5, wherein K=1 in at least one loop of the M loops.

9. The method of claim 1, wherein a first loop of the M loops comprises a first interposer channel of the N interposer channels, wherein the first interposer channel comprises a first channel segment and a second channel segment, and wherein the first channel segment is about perpendicular to the second channel segment.

10. The method of claim 1, wherein each substrate channel of the N substrate channels has a larger flow area than each interposer channel of the N interposer channels.

11. The method of claim 1, wherein the interposer is thermally coupled to the heat sink by a thermally conductive cover that is sandwiched between the heat sink and the interposer.

12. The method of claim 11, wherein the cover is in direct mechanical contact with the heat sink.

13. The method of claim 1, wherein a coefficient of thermal expansion (CTE) of the interposer is substantially equal to a CTE of the substrate.

14. The method of claim 1, wherein the N substrate channels and the N interposer channels are hermetically sealed with a vacuum therein.

15. The method of claim 13, wherein the structure comprises the heat sink, wherein the interposer is thermally coupled to the heat sink, wherein a fluid partially but not totally fills each substrate channel of the N substrate channels and each interposer channel of the N interposer channels, wherein the fluid is adapted to transfer heat from the heat source to the interposer, and wherein the fluid is adapted to transfer a portion of said heat from the interposer to the heat sink.

16. The method of claim 1, wherein the substrate comprises a semiconductor chip, wherein the semiconductor chip comprises active electronic devices on a second side of the substrate that is opposite the first side of the substrate, and wherein the heat source comprises the active electronic devices.

17. The method of claim 16, wherein the semiconductor chip is partially but not totally embedded within the interposer, and wherein a portion of the semiconductor chip is mechanically and thermally coupled to the interposer by a thermally conductive sealant therebetween.

18. The method of claim 16, wherein the structure comprises the heat sink.

19. The method of claim 16, wherein the structure comprises the heat sink and a thermally conductive cover that is sandwiched between the heat sink and the interposer, wherein the interposer is thermally coupled to the heat sink by the cover that is sandwiched between the heat sink and the interposer, and wherein a CTE of the cover is substantially equal to a CTE of the semiconductor chip.

20. The method of claim 19, wherein a CTE of the interposer is substantially equal to the CTE of the semiconductor chip.