ERROR RECOVERY STORAGE ALONG A NAND-FLASH STRING

• US 20090013233A1
• Filed: 07/06/2007
• Published: 01/08/2009
• Est. Priority Date: 07/06/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Radke, William H.
• Granted Patent: US 8,051,358 B2
• Time in Patent Office: Days
• US Class Current: 714/752
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: H03M 13/256 with trellis coding, e.g. with convolutional codes and TCM
• CPC Class Codes: H03M 13/2909 Product codes

Abstract

Apparatus and methods store error recovery data in different dimensions of a memory array. For example, in one dimension, block error correction codes (ECC) are used, and in another dimension, supplemental error correction codes, such as convolutional codes, are used. By using separate dimensions, the likelihood that a defect affects both error recovery techniques is lessened, thereby increasing the probability that error recovery can be performed successfully. In one example, block error correction codes are used for data stored along rows, and this data is stored in one level of multiple-level cells of the array. Supplemental error correction codes are used for data stored along columns, such as along the cells of a string, and the supplemental error correction codes are stored in a different level than the error correction codes.

Claims

1. A method of storing error recovery data for a NAND flash memory array having two or more levels, the method comprising:

storing data with a block error correction code using a first level of multiple-level cells and along a first dimension of the NAND flash memory array; and

storing data with a supplemental error correction code using a second level of the multiple-level cells and along a second dimension of the NAND flash memory array, wherein the supplemental error correction code is incrementally updateable.

2. The method of claim 1, wherein the supplemental error correction code comprises a convolutional code.

3. The method of claim 1, wherein the supplemental error correction code comprises a partial-response, maximum likelihood (PRML) code.

4. The method of claim 1, wherein the supplemental error correction code comprises trellis-coded modulation (TCM).

5. The method of claim 1, wherein the first dimension is along a row of the NAND flash memory array, the method further comprising computing a block error correction code for the error correction code.

6. The method of claim 1, wherein the second dimension is along a column of the NAND flash memory array, the method further comprising computing a supplemental error correction code stored in a first level of a previously-written row and current data to be stored.

7. The method of claim 6, wherein computing the supplemental error correction code comprises computing a convolutional code, the method further comprising:

computing an exclusive-OR (XOR) of a data bit to be stored in the first level of a first cell of a NAND flash string with a data bit stored in the first level of a second cell of the NAND flash logically adjacent to the first cell; and

storing the computed data bit in the second level of the first cell.

8. The method of claim 1, further comprising:

receiving a first page of data to be stored in the NAND flash memory array;

retrieving one or more pages of data corresponding to data that has already been written to the NAND flash memory array; and

computing the supplemental error correction code based on data for the first page and the second page.

9. A method of recovering data from a NAND flash memory array, the method comprising:

reading a page of data from a first selected row of the memory array;

performing block decoding of error correction codes of the page of data;

determining that error exists after block decoding of the page of data; and

decoding supplemental error correction codes relating to the first selected row to recover the page of data, wherein the supplemental error correction codes are arranged along columns of the memory array, wherein the supplemental error correction codes are incrementally updateable.

10. The method of claim 9, wherein the supplemental error correction codes comprise convolutional codes.

11. The method of claim 9, wherein the supplemental error correction codes comprise partial-response, maximum likelihood (PRML) codes.

12. The method of claim 9, wherein the supplemental error correction codes comprise trellis-coded modulation (TCM).

13. The method of claim 9, further comprising performing block decoding of error correction codes of the page of data.

14. The method of claim 9, wherein decoding supplemental error correction codes further comprises:

reading the page of data from a first level of the first selected row of the memory array;

retrieving a supplemental error correction code stored on a second level of the first selected row of the memory array;

retrieving another page of data from a row that is logically adjacent to the first selected row; and

decoding the supplemental error correction codes.

15. The method of claim 14, wherein decoding comprises performing exclusive-OR (XOR) operations of data bits retrieved from the second level of the first selected row with data bits retrieved from the first level of the logically adjacent row.

16. The method of claim 9, wherein decoding supplemental error correction codes further comprises:

retrieving another page of data from a row that is logically adjacent to the first selected row;

retrieving a supplemental error correction code stored on a second level of the logically adjacent row of the memory array; and

decoding the supplemental error correction codes.

17. The method of claim 9, further comprising decoding at least partially in response to the determination of error.

18. An apparatus comprising:

an interface circuit configured to receive data intended for storage to a memory device and to communicate with the memory device, wherein data for the memory device is stored in rows and columns of a NAND flash memory array, and wherein cells of the NAND flash memory array store data in at least two levels; and

a supplemental error correction coder circuit coupled to the interface circuit, the supplemental error correction coder circuit configured to compute supplemental error correction codes by columns of data, wherein the supplemental error correction codes are incrementally updateable.

19. The apparatus of claim 18, wherein the supplemental error correction codes comprise convolutional codes.

20. The apparatus of claim 18, wherein the supplemental error correction codes comprise partial-response, maximum likelihood (PRML) codes.

21. The apparatus of claim 18, wherein the supplemental error correction codes comprise trellis-coded modulation (TCM).

22. The apparatus of claim 18, wherein the interface circuit is configured to store the received data in a first level of the array of the memory device, and to store supplemental error correction coded data on a level other than the first level.

23. The apparatus of claim 18, wherein the supplemental error correction coder circuit is configured to compute an exclusive-OR (XOR) of the received data and data from a logically adjacent row of the NAND flash memory array, wherein the logically adjacent row is logically adjacent to an intended row for the received data.

24. The apparatus of claim 23, wherein the interface circuit is configured to store the received data in a first level of the array of the memory device, and to store the XOR data on a level other than the first level.

25. The apparatus of claim 23, wherein the XOR computation is not performed for a first selected row of a string of memory cells for the array of the memory device.

26. The apparatus of claim 18, further comprising a supplemental decoder for decoding of the supplemental error correction codes.

27. The apparatus of claim 18, further comprising:

an ECC coder for generation of block error correction codes;

an ECC decoder for decoding of block error correction codes; and

a selection circuit configured to select between data retrieved from the memory array without decoding of supplemental error correction codes and data as recovered from decoding of supplemental error correction codes at least partially based on whether the data was decoded by block error correction codes with error.

28. An apparatus comprising:

an interface circuit configured to receive data intended for storage to a memory device and to communicate with the memory device, wherein data for the memory device is stored in rows and columns of a NAND flash memory array, and wherein cells of the NAND flash memory array store data in at least two levels; and

a supplemental decoder circuit coupled to the interface circuit, the supplemental decoder circuit configured to decode supplemental error correction codes to recover data, wherein the supplemental error correction codes are incrementally updateable.

29. The apparatus of claim 28, wherein the supplemental error correction codes comprise convolutional codes.

30. The apparatus of claim 28, wherein the supplemental error correction codes comprise partial-response, maximum likelihood (PRML) codes.

31. The apparatus of claim 28, wherein the supplemental error correction codes comprise trellis-coded modulation (TCM).

32. The apparatus of claim 28, wherein the interface circuit is configured to retrieve data without supplemental error correction codes from a first level of the array of the memory device, and to retrieve supplemental error correction coded data on a level other than the first level.

33. An apparatus comprising:

a NAND flash memory array having rows and columns, wherein each cell of the NAND flash memory stores at least two bits of data, wherein data is written to and read from the NAND flash memory array in rows;

a supplemental error correction coding circuit configured to compute supplemental error correction codes by columns of normal data; and

a supplemental decoding circuit configured to decode supplemental error correction codes stored in the NAND flash memory array to recover data, wherein the supplemental error correction codes are incrementally updateable.

34. The apparatus of claim 33, wherein the supplemental error correction codes comprise convolutional codes.

35. The apparatus of claim 33, wherein the supplemental error correction codes comprise partial-response, maximum likelihood (PRML) codes.

36. The apparatus of claim 33, wherein the supplemental error correction codes comprise trellis-coded modulation (TCM).

37. The apparatus of claim 33, wherein normal data is written in a first level of the NAND flash memory array, and the supplemental error correction codes are written in a second level of the NAND flash memory array.

38. The apparatus of claim 33, wherein the supplemental error correction coding circuit comprises a convolutional coder, a data store, and a write buffer, and wherein the supplemental decoding circuit comprises a deconvolver, a data store, and a read buffer.

39. The apparatus of claim 33, further comprising a block error correction code generation circuit configured to compute block error correction codes for normal data and a block error correction code decoding circuit configured to correct errors in normal data.

40. The apparatus of claim 39, wherein the block error correction code decoding circuit is configured to correct errors in the recovered data from the supplemental decoding circuit.

41. The apparatus of claim 39, further comprising a data selector, wherein the data selector is configured to select between the normal data and recovered data depending on results from the block error correction code decoding circuit.