SEMICONDUCTOR DEVICE

• US 20090014770A1
• Filed: 07/09/2008
• Published: 01/15/2009
• Est. Priority Date: 07/12/2007
• Status: Active Grant

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Terao, Motoyasu, Sasago, Yoshitaka, Takemura, Riichiro, Takaura, Norikatsu, Matsuoka, Hideyuki, Irie, Naohiko
• Granted Patent: US 7,829,930 B2
• Time in Patent Office: Days
• US Class Current: 257/314
• CPC Class Codes: G11C 11/5614 using conductive bridging RAM [CBRAM] or programming metallization cells [PMC]
• CPC Class Codes: G11C 13/0011 comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
• CPC Class Codes: G11C 2213/11 Metal ion trapping, i.e. using memory material including cavities, pores or spaces in form of tunnels or channels wherein metal ions can be trapped but do not react and form an electro-deposit creating filaments or dendrites
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/245 the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8416 adapted for supplying ionic species
• CPC Class Codes: H10N 70/8822 Sulfides, e.g. CuS
• CPC Class Codes: H10N 70/8825 Selenides, e.g. GeSe
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/883 Oxides or nitrides
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx

Abstract

A technique that can realize high integration even for multilayered three-dimensional structures at low costs by improving the performance of the semiconductor device having recording or switching functions by employing a device structure that enables high precision controlling of the movement of ions in the solid electrolyte. The semiconductor element of the device is formed as follows; two or more layers are deposited with different components respectively between a pair of electrodes disposed separately in the vertical (z-axis) direction, then a pulse voltage is applied between those electrodes to form a conductive path. The resistance value of the path changes according to an information signal. Furthermore, a region is formed at a middle part of the conductive path. The region is used to accumulate a component that improves the conductivity of the path, thereby enabling the resistance value (rate) to response currently to the information signal. More preferably, an electrode should also be formed at least in either the x-axis or y-axis direction to apply a control voltage to the electrode.

Claims

1. A semiconductor device, comprising:

a first electrode formed on a semiconductor substrate;

a second electrode formed on the semiconductor substrate so as to face the first electrode; and

a laminated film formed between the first and second electrodes and consisting of at least two stacked solid electrolytic layers of which components differ from each other,

wherein the first electrode includes a metal to be diffused in the solid electrolytic layer so as to form a low resistance conductive path therein; and

wherein the solid electrolytic laminated film is formed so that the mobility of the solid electrolytic layer closer to the first electrode with respect to the metal becomes higher than that of the solid electrolytic layer closer to the second electrode with respect to the metal.

2. The semiconductor device according to claim 1,

wherein the direction of the high conductivity path formed in the solid electrolytic laminated layer connecting the first and second electrodes to each other is assumed as a Z-axis direction;

and

wherein the X-axis direction electrode is formed at one side or both sides of the conductive path so as to sandwich the conductive path therebetween in the X-axis direction that is approximately orthogonal to the Z-axis direction.

3. The semiconductor device according to claim 2,

wherein the device further includes means that applies a voltage to the x-axis direction electrode, thereby controlling the resistance value of the conductor path.

4. The semiconductor device according to claim 2,

wherein Y-axis direction electrodes are disposed at both sides of the conductive path so as to sandwich the conductive path therebetween in the Y-axis direction that is approximately orthogonal to the X-axis and Z-axis directions respectively.

5. The semiconductor device according to claim 4,

wherein the device further includes means that keeps the distribution of a conductivity improving material accumulated in the conductive path in a constant state when a voltage is applied to at least either the X-axis or Y-axis direction electrode to repetitively raise and lower the resistance value of the conductive path.

6. The semiconductor device according to claim 4,

wherein the means that keeps the constant state is the X-axis direction electrode disposed near an end of the conductive path around either the first or the second electrode.

7. The semiconductor device according to claim 1,

wherein the device further includes a region that accumulates a conductivity improving material in the middle of the conductive path;

and

wherein the device further includes means that relates the resistance value in the conductivity improving material accumulating region to an information signal, thereby identifying the information signal according to the resistance value.

8. The semiconductor device according to claim 4,

wherein code conversion is carried out each time information is to be recorded in the conductive path so that the average value of recorded information is almost fixed in each memory cell, thereby avoiding that the conductivity improving material is accumulated unevenly among memory cells after multiple rewriting operations of information recorded in the conductive path.

9. The semiconductor device according to claim 1,

wherein the device includes a plurality of pairs of the first and second electrodes;

and

wherein the conductive path has an angle deviated from a direction in which the pair of first and second electrodes are connected to each other at least in its middle portion.

10. The semiconductor device according to claim 9,

wherein the device includes a plurality of the conductive paths;

wherein the device further includes means that switches or branches one of those conductive paths to a path having a different angle.

11. The semiconductor device according to claim 10,

wherein the switching means is provided in each solid electrolytic layer and has a pair of electrodes that are disposed so as to sandwich the conductor path therebetween.

12. The semiconductor device according to claim 10,

wherein a phase boundary region between the conductor path and the region having an angle from the conductive path functions as an information memory.

13. The semiconductor device according to claim 4,

wherein a voltage is applied between an electrode disposed at either end of the corresponding conductive path and a Y-axis direction electrode provided near the conductive path upon reading information stored in the conductor path, thereby detecting the stored information according to the value of the resistance between those electrodes.

14. The semiconductor device according to claim 4,

wherein a voltage is applied to a Y-axis direction electrode disposed near the corresponding conductive path upon reading information stored in the conductive path, thereby detecting information stored in the conductive path according to an electromotive force generated in the X-axis direction electrode.

15. The semiconductor device according to claim 4,

wherein a voltage is applied to the corresponding conductive path upon reading information stored in the conductive path, thereby detecting information stored in the conductive path according to the electromotive force generated in the X-axis direction electrode or Y-axis direction electrode disposed near the conductive path.

16. The semiconductor device according to claim 4,

wherein the device further includes means that controls the resistance between the pair of electrodes or a pair of electrodes disposed closely to the pair of electrodes, with use of multiple values according to the number of write pulses or the pulse width.

17. A semiconductor device, comprising:

a first electrode provided on a semiconductor substrate and having a first conductivity;

a second electrode provided on the semiconductor substrate so as to face the first electrode and having a second conductivity; and

a laminated film formed between the first and second electrodes and consisting of at least two stacked solid electrolytic layers,

wherein the first electrode includes a metal to be diffused in the solid electrolyte laminated layer to form a low resistance path therein; and

a phase boundary layer provided between each pair of solid electrolyte layers and having mobility lower than that of each of the first and second solid electrolyte layers.

18. The semiconductor device according to claim 17,

wherein the phase boundary layer is 1 nm to 10 nm in film thickness.

19. The semiconductor device according to claim 17;

wherein at least one of the phase boundary layers between the pairs of solid electrolyte layers respectively has a phase boundary layer of which oxygen or nitrogen concentration is high.

20. The semiconductor device according to claim 17,

wherein components of non-metal elements contained in the solid electrolyte laminated layer are those listed up from top to bottom sequentially beginning at the first electrode side in the periodic law table.

21. A semiconductor device, comprising:

a first electrode provided on a semiconductor substrate;

a second electrode provided on the semiconductor substrate so as to face the first electrode; and

a laminated film formed between the first and second electrodes and consisting of at least two stacked solid electrolyte layers having different components respectively,

wherein the first electrode includes a metal to be diffused in the solid electrolyte layer to form a low resistance path therein; and

wherein the first electrode consists of at least one element selected from a group consisting of Cu, Ag, Zn, Cd, and Al and the second element consists of at least one element selected from a group consisting of W, Ta, Mo, Nb, Cr, Ni, Ti, and Pt group elements, as well as Ti nitride; and

wherein the solid electrolyte layer is a laminated film consisting of two or more layers having different components respectively, in which one of those layers is an oxide layer composed of at least one element selected from a group consisting of Cu, Ag, Zn, Cd, and Al, as well as at least one element selected from a group consisting of Ta, Mo, Nb, Cr, Ni, Co, Ti, and Pt group elements, and the other of those layers is a layer composed of at least one component selected from a group consisting of O, S, Se, and Te.

22. The semiconductor device according to claim 21,

wherein the first electrode is made of an oxide that includes Cu or made of chalcogenide;

and

wherein the second electrode is made of at least one element selected from a group consisting of W, Ta, Mo, Nb, Cr, Ni, Co, Ti, and Pt group elements, as well as Ti nitride.

23. A semiconductor device, comprising:

a first electrode provided on a semiconductor substrate and having first mobility;

a second electrode provided on the semiconductor substrate so as to face the first electrode and having second mobility; and

a laminated film formed between the first and second electrodes and consisting of at least two stacked solid electrolyte layers,

wherein the first electrode includes a metal to be diffused in the solid electrolyte layer to form a low resistance path therein;

wherein the first electrode is made of Cu and the second electrode is made of W or Pt;

wherein the phase boundary layer is made of Al₂O₃; and

wherein the solid electrolyte laminated layer is a multilayer film consisting of a chalcogenide layer containing Cu—

Ta—

O and a chalcogenide layer containing Cu—

Ta—

S.

24. The semiconductor device according to claim 23,

wherein the first electrodes is made of an oxide containing Cu or chalcogenide;

wherein the second electrode is made of at least one element selected from a group consisting of W, Ta, Mo, Nb, Cr, Ni, Co, Ti, and Pt group elements, as well as Ti nitride.

25. A semiconductor device, comprising:

a first electrode provided on a semiconductor substrate;

a second electrode provided on the semiconductor substrate so as to face the first electrode; and

a laminated film formed between the first and second electrodes and consisting of at least two stacked solid electrolyte layers having different components respectively,

wherein the first electrode includes a metal to be diffused in the solid electrolyte layer to form a low resistance path therein;

wherein the first electrode is made of at least one element selected from a group consisting of Cu, Ag, Zn, Cd, and Al while the second electrode is made of at least one element selected from a group consisting of W, Ta, Mo, Nb, Cr, Ni, Co, Ti, and Pt group elements, as well as Ti nitride;

wherein the solid electrolyte layer is a multilayer film consisting of two or more layers having different compositions respectively, the multilayer film including an oxide layer composed of at least one element selected from a group consisting of Cu, Ag, Zn, Cd, and Al or at least one element selected from a group consisting of Ta, Mo, Nb, Cr, Ni, Co, Ti, and Pt group elements and O, and another layer composed of at least one component selected from a group consisting of Cu, Ag, Zn, Cd, and Al or at least one element selected from a group consisting of Ta, Mo, Nb, Cr, Ni, Co, Ti, and Pt group elements and at least one element selected from a group consisting of O, S, Se, and Te.