Multi-Layer Semiconductor Structure and Manufacturing Method Thereof

• US 20090014787A1
• Filed: 01/04/2008
• Published: 01/15/2009
• Est. Priority Date: 07/11/2007
• Status: Abandoned Application

• Current Assignee: ProMOS Technologies, Inc.
• Original Assignee: ProMOS Technologies, Inc.
• Inventors: Wang, Ting Sing
• Application Number:
  US11/969,702
• Publication Number:
  US 20090014787A1
• Time in Patent Office: Days
• US Class Current: 257/331
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4941 with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A power MOSFET structure comprises at least one first gate in the cell area and at least one second gate at the peripheral that are both in a semiconductor substrate. The first and second gates are electrically connected, and the second gate is connected to a contact so as to electrically connect to a bond pad for transmitting gate control signals. The semiconductor substrate comprises a first semiconductor layer, a second semiconductor layer and a third semiconductor layer in downward sequence. The first and third semiconductor layers are of a first conductive type, e.g., n-type, and the second semiconductor layer is of a second conductive type, e.g., p-type. The first and third semiconductor layers serve as the source and the drain, respectively.

Claims

1. A power metal-oxide-semiconductor field effect transistor (MOSFET) structure, comprising:

at least one first gate placed in a cell area of a die and formed in a semiconductor substrate;

at least one second gate placed at the peripheral of the die and formed in the semiconductor substrate;

wherein the first and second gates are electrically connected, and the second gate are connected to a contact connecting to a first bonding pad to transmit gate control signals.

2. The power MOSFET structure in accordance with claim 1, further comprising a gate oxide layer between the first and second gates and the semiconductor substrate.

3. The power MOSFET structure in accordance with claim 1, wherein the contact is a tungsten plug.

4. The power MOSFET structure in accordance with claim 3, further comprising a titanium metal liner between the tungsten plug and the second gate.

5. The power MOSFET structure in accordance with claim 3, wherein the tungsten plug is connected to an aluminum-copper metal layer.

6. The power MOSFET structure in accordance with claim 3, wherein the bottom of the tungsten plug is connected to an ion implantation region.

7. The power MOSFET structure in accordance with claim 1, wherein the semiconductor substrate comprises from top to bottom a first semiconductor layer, a second semiconductor layer and a third semiconductor layer, the first and third semiconductor layers being of a first conductive type, the second semiconductor layer being of a second conductive type, and the first and third semiconductor layers serving respectively as a source and a drain of the power MOSFET.

8. The power MOSFET structure in accordance with claim 7, wherein the first semiconductor layer is electrically connected to a second bonding pad through a conductive connection for transmitting source control signals.

9. The power MOSFET structure in accordance with claim 8, wherein the conductive connection is a tungsten plug.

10. The power MOSFET structure in accordance with claim 9, wherein the bottom of the tungsten plug is connected to an ion implantation region.

11. The power MOSFET structure in accordance with claim 7, further comprising a guard ring formed in the second semiconductor layer, the guard ring being of the second conductive type, and the polarity of the guard ring being opposite to that of the second semiconductor layer.

12. The power MOSFET structure in accordance with claim 11, wherein the guard ring is electrically connected to a second bonding pad through a metal connection for transmitting source control signals.

13. A method for manufacturing a power MOSFET, comprising:

forming at least one first trench and at least one second trench in a semiconductor substrate, wherein the first trench is in a cell area of a die and the second trench is at the peripheral of the die;

filling a conductive layer in the first trench and the second trench to form a first gate and a second gate, wherein the first and second gates are electrically connected;

forming a dielectric layer on the first and second gates and the semiconductor substrate; and

forming a contact penetrating through the dielectric layer to the second gate, the contact being electrically connected to a first bonding pad for transmitting gate control signals.

14. The method in accordance with claim 13, wherein the width of the second trench is greater than that of the first trench.

15. The method in accordance with claim 13, wherein the depths of the first trench and the second trench are between 1.2 and 1.4 μ

m.

16. The method in accordance with claim 13, wherein the first gate and the second gate are formed by filling a polysilicon layer and then planarization.

17. The method in accordance with claim 16, wherein the planarization performs chemical mechanical polishing.

18. The method in accordance with claim 13, wherein the semiconductor substrate comprises from top to bottom a first semiconductor layer, a second semiconductor layer and a third semiconductor layer, the first and third semiconductor layers being of a first conductive type, the second semiconductor layer being of a second conductive type, and the first and third semiconductor layers respectively serve as the source and the drain of the power MOSFET.

19. The method in accordance with claim 18, wherein a conductive connection connected to the first semiconductor layer is formed at the same time when the contact is formed, and the conductive connection is electrically connected to a second bonding pad for transmitting source control signals.

20. The method in accordance with claim 13, wherein forming the dielectric layer comprises the steps of forming a silicon-rich oxide layer and an oxidation layer in sequence.

21. The method in accordance with claim 13, further comprising a step of forming an aluminum-copper metal layer connecting to the top of the contact.

22. The method in accordance with claim 18, wherein a metal connection connected to a guard ring of the second semiconductor layer is formed at the same time when the contact is formed, the guard ring being of a second conductive type, and the polarity of the guard ring being opposite to that of the second conductive layer.

23. The method in accordance with claim 22, wherein the guard ring is electrically connected to a second bonding pad for transmitting source control signals.