Semiconductor Device with Reduced Capacitance Tolerance Value

• US 20090014832A1
• Filed: 07/09/2007
• Published: 01/15/2009
• Est. Priority Date: 07/09/2007
• Status: Abandoned Application

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Baumgartner, Peter, Riess, Philipp, Benetik, Thomas
• Application Number:
  US11/775,086
• Publication Number:
  US 20090014832A1
• Time in Patent Office: Days
• US Class Current: 257/532
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device includes a capacitance, the numerical value of which is relevant for a device function. The capacitance is formed from a parallel connection of at least a first and a second capacitor element, wherein the first and second capacitor elements are formed in respective manufacturing steps that exhibit uncorrelated process fluctuations.

Claims

1. A semiconductor device, comprising a capacitance, the numerical value of which is relevant for a device function, wherein the capacitance comprises a parallel connection of at least a first capacitor element and a second capacitor element, wherein the first and second capacitor elements are formed in respective manufacturing steps that exhibit uncorrelated process fluctuations.

2. The semiconductor device of claim 1, wherein the capacitance comprises a parallel connection of more than two capacitor elements, wherein the capacitor elements are formed in respective manufacturing steps that exhibit uncorrelated process fluctuations.

3. The semiconductor device of claim 1, wherein a first capacitance value of the first capacitor element and a second capacitance value of the second capacitor element, to obtain a predetermined total capacitance value, are selected such that a process tolerance of the capacitance is minimized.

4. The semiconductor device of claim 3, wherein, if a first process tolerance value is equal to a second process tolerance value, the first capacitance value is selected equal to the second capacitance value.

5. The semiconductor device of claim 2, wherein respective capacitance values of the capacitor elements connected in parallel and each having a respective capacitance tolerance value are, to obtain a predetermined total capacitance value, selected such that a tolerance value of a resulting capacitance is minimized.

6. The semiconductor device of claim 1, wherein the first capacitor element comprises an MIM capacitor element and the second capacitor element comprises a BEOL capacitor element.

7. The semiconductor device of claim 1, wherein the first capacitor element comprises an MIM capacitor element and the second capacitor element comprises an MOS capacitor element.

8. The semiconductor device of claim 1, wherein the first capacitor element comprises an MIM capacitor element containing a first type of dielectric layer and the second capacitor element comprises an MIM capacitor element containing a second type of dielectric layer.

9. The semiconductor device of claim 1, wherein the first capacitor element comprises a sandwich-type BEOL capacitor element and the second capacitor element comprises a GRID-type BEOL capacitor element.

10. The semiconductor device of claim 1, wherein the first capacitor element comprises a sandwich-type BEOL capacitor element and the second capacitor element comprises a VPP-type BEOL capacitor element.

11. The semiconductor device of claim 1, wherein the first capacitor element comprises a GRID-type BEOL capacitor element and the second capacitor element comprises a VPP-type BEOL capacitor element.

12. The semiconductor device of claim 1, wherein the first capacitor element comprises an MOS capacitor element containing a first type of oxide layer and the second capacitor element comprises an MOS capacitor element containing a second type of oxide layer.

13. The semiconductor device of claim 2, wherein the first capacitor element comprises an MIM capacitor element, the second capacitor element comprises a BEOL capacitor element, and a third capacitor element comprises an MOS capacitor element.

14. The semiconductor device of claim 2, wherein the respective capacitor elements are MIM capacitor elements containing different types of dielectric layers.

15. The semiconductor device of claim 2, wherein the respective capacitor elements comprise different types of BEOL capacitor elements selected from the group consisting of sandwich capacitor elements, GRID capacitor elements, and VPP capacitor elements.

16. The semiconductor device of claim 2, wherein the respective capacitor elements comprise MOS capacitor elements containing different types of oxide layers.

17. The semiconductor device of claim 2, wherein the capacitance comprises a parallel connection of at least two sandwich capacitor elements, produced in different process steps, and at least two VPP capacitor elements, produced in different process steps, of a BEOL stack.

18. The semiconductor device of claim 2, wherein the capacitance comprises a parallel connection of at least two BEOL capacitor elements of different type and at least one MOS capacitor element.

19. The semiconductor device of claim 2, wherein the capacitance comprises a parallel connection of at least one BEOL capacitor element and at least two MOS capacitor elements, the MOS capacitor elements containing different types of oxide layers.

20. The semiconductor device of claim 6, wherein the first capacitor element comprises at least one aluminum or copper layer and at least one layer of a material selected from the group consisting of TiN, TaN, ONO, SiO₂, Ta₂O₅, Al₂O₃, and HfO.

21. The semiconductor device of claim 7, wherein the first capacitor element comprises a first aluminum layer forming a top capacitor plate and a second aluminum layer forming a bottom capacitor plate, the first capacitor further comprising at least one layer of a material selected from the group consisting of TiN, TaN, ONO, SiO₂, Ta₂O₅, Al₂O₃, and HfO.

22. The semiconductor device of claim 6, wherein the second capacitor element comprises a stack of sandwich metal layers.

23. The semiconductor device of claim 9, wherein the second capacitor element comprises a stack of sandwich metal layers.

24. The semiconductor device of claim 11, wherein the second capacitor element comprises a stack of sandwich metal layers.

25. The semiconductor device of claim 1, comprising a voltage controlled oscillator wherein the numerical value of the capacitance determines an oscillator frequency.

26. The semiconductor device of claim 1, comprising an analog/digital converter wherein the numerical value of the capacitance determines conversion characteristics.

27. The semiconductor device of claim 1, comprising a filter portion wherein the numerical value of the capacitance determines a filter characteristic.

28. A semiconductor voltage controlled oscillator, comprising a capacitance the numerical value of which determines an oscillator frequency, wherein the capacitance comprises a parallel connection of at least a first and a second capacitor element, wherein the first and second capacitor elements are formed in respective manufacturing steps that exhibit uncorrelated process fluctuations, and wherein a first capacitance value of the first capacitor element and a second capacitance value of the second capacitor element, to obtain a predetermined total capacitance value, are selected such that a process tolerance of the capacitance is minimized.

29. The semiconductor voltage controlled oscillator of claim 28, wherein the first capacitor element comprises an MIM capacitor element and the second capacitor element comprises a BEOL capacitor element.

30. An analog/digital semiconductor converter, comprising a capacitance the numerical value of which determines a converting characteristic, wherein the capacitance comprises a parallel connection of at least a first and a second capacitor element, wherein the first and second capacitor elements are formed in respective manufacturing steps that exhibit uncorrelated process fluctuations, and wherein a first capacitance value of the first capacitor element and a second capacitance value of the second capacitor element, to obtain a predetermined total capacitance value, are selected such that a process tolerance of the capacitance is minimized.

31. The analog/digital semiconductor converter of claim 30, wherein the first capacitor element comprises an MIM capacitor element and the second capacitor element comprises a BEOL capacitor element.

32. A semiconductor filter device, comprising a capacitance the numerical value of which determines a filter characteristic, wherein the capacitance comprises a parallel connection of at least a first and a second capacitor element, wherein the first and second capacitor elements are formed in respective manufacturing steps which exhibit uncorrelated process fluctuations, and wherein a first capacitance value of the first capacitor element and a second capacitance value of the second capacitor element, to obtain a predetermined total capacitance value, are selected such that a process tolerance of the capacitance is minimized.

33. The semiconductor filter device of claim 32, wherein the first capacitor element comprises an MIM capacitor element and the second capacitor element comprises a BEOL capacitor element.

34. An MOS type semiconductor device, comprising a capacitance the numerical value of that affects a device function, wherein the capacitance comprises a parallel connection of at least a first and second capacitor element, wherein the first capacitor element comprises an MOS capacitor element and the second capacitor element is formed in a manufacturing step that exhibits process fluctuations that are uncorrelated to the process fluctuations of MOS manufacturing steps, and wherein a first capacitance value of the first capacitor element and a second capacitance value of the second capacitor element, to obtain a predetermined total capacitance value, are selected such that a process tolerance of the capacitance is minimized.

35. The MOS type semiconductor device of claim 34, wherein the second capacitor element comprises an MIM capacitor element.

36. The MOS type semiconductor device of claim 34, wherein the second capacitor element comprises a BEOL capacitor element.

37. The MOS type semiconductor device of claim 34, wherein the capacitance comprises a parallel connection of more than two capacitor elements, wherein a first capacitor element is an MOS capacitor element and the further capacitor elements are formed in respective manufacturing steps that exhibit uncorrelated process fluctuations with the MOS manufacturing steps.

38. The MOS type semiconductor device of claim 37, wherein a second capacitor element comprises a BEOL capacitor element and a third capacitor element comprises an MIM capacitor element.

39. An MOS type semiconductor device, comprising a capacitance the numerical value of which is relevant for a device function, wherein the capacitance comprises a parallel connection of at least a first and second capacitor element, wherein the first capacitor element comprises an MOS capacitor element containing an oxide layer of a first type or thickness, respectively, and the second capacitor element contains an oxide layer of a second type or thickness, respectively, and wherein a first capacitance value of the first capacitor element and a second capacitance value of the second capacitor element, to obtain a predetermined total capacitance value, are selected such that a process tolerance of the capacitance is minimized.