SEMICONDUCTOR WAFER STRUCTURE

• US 20090014857A1
• Filed: 07/13/2007
• Published: 01/15/2009
• Est. Priority Date: 07/13/2007
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Hufgard, Erich
• Granted Patent: US 8,198,713 B2
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06575 Auxiliary carrier between devices, the carrier having no electrical connection structure
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/1433 Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/1461 MEMS
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding

Abstract

One embodiment provides a semiconductor wafer structure including a semiconductor wafer and a spacer layer. The semiconductor wafer includes active areas. The spacer layer is configured to provide spacing between the semiconductor dice in a stacked die package and the spacer layer is disposed on one side of the semiconductor wafer.

Claims

1. A semiconductor wafer structure, comprising:

a semiconductor wafer including active areas; and

a spacer layer configured to provide spacing between semiconductor dice in a stacked die package, wherein the spacer layer is disposed on one side of the semiconductor wafer.

2. The semiconductor wafer structure of claim 1, wherein the semiconductor wafer includes the active areas on the one side and the spacer layer is disposed over the active areas on the one side.

3. The semiconductor wafer structure of claim 1, wherein the one side is the back side of the semiconductor wafer.

4. The semiconductor wafer structure of claim 1, wherein the spacer layer is disposed as a solid piece of material on the semiconductor wafer.

5. The semiconductor wafer structure of claim 4, wherein the solid piece of material is attached to the semiconductor wafer via one of an adhesive, solder, and anodic bonding.

6. The semiconductor wafer structure of claim 1, wherein the spacer layer is disposed as a fluid on the semiconductor wafer.

7. The semiconductor wafer structure of claim 6, wherein the fluid is disposed on the semiconductor wafer via one of immersion dipping, spraying, and spin coating.

8. The semiconductor wafer structure of claim 1, wherein the spacer layer is patterned in one of a wafer level process before being disposed on the one side of the semiconductor wafer and a wafer level process after being disposed on the one side of the semiconductor wafer.

9. The semiconductor wafer structure of claim 1, wherein the spacer layer is patterned via one of photolithographic processing and etching, and photo ablation.

10. The semiconductor wafer structure of claim 1, wherein the spacer layer is patterned via a mechanical treatment.

11. The semiconductor wafer structure of claim 10, wherein the mechanical treatment includes one of sawing, milling, grinding, punching, molding, casting, and drilling.

12. A semiconductor device, comprising:

a semiconductor die from a semiconductor wafer including active areas; and

a spacer on the semiconductor die, wherein the spacer is a singulated piece from a spacer layer disposed on one side of the semiconductor wafer.

13. The semiconductor device of claim 12, wherein the semiconductor wafer and the spacer layer are singulated in different process steps to provide the semiconductor die and the spacer.

14. The semiconductor device of claim 12, wherein the semiconductor wafer and the spacer layer are singulated in substantially the same process step to provide the semiconductor die and the spacer.

15. The semiconductor device of claim 12, wherein the spacer is patterned via photolithographic processing and etching in a wafer level process.

16. The semiconductor device of claim 12, wherein the spacer is patterned via mechanical treatment in a wafer level process.

17. A stacked die package, comprising:

a first semiconductor die from a semiconductor wafer including active areas;

a second semiconductor die; and

a spacer disposed on the first semiconductor die and configured to provide spacing between the first semiconductor die and the second semiconductor die in the stacked die package, wherein the spacer is a singulated piece of a spacer layer disposed on one side of the semiconductor wafer.

18. The stacked die package of claim 17, wherein the spacer is patterned in a wafer level process to extend between bond pads of the first semiconductor die.

19. The stacked die package of claim 17, wherein the spacer is patterned in a wafer level process to extend between bond pads of the second semiconductor die.

20. A semiconductor structure, comprising:

means for spacing semiconductor dice in a stacked die package disposed on one side of a semiconductor wafer including active areas.

21. The semiconductor structure of claim 20, wherein the means for spacing comprises:

means for spacing disposed over the active areas of the semiconductor wafer.

22. The semiconductor structure of claim 20, wherein the means for spacing comprises:

means for spacing disposed over the back side of the semiconductor wafer.

23. The semiconductor structure of claim 20, wherein the means for spacing comprises:

means for spacing disposed as a solid piece of material on the semiconductor wafer.

24. The semiconductor structure of claim 20, wherein the means for spacing comprises:

means for spacing disposed as a fluid on the semiconductor wafer.

25. A method of packaging semiconductor dice, comprising:

providing semiconductor dice in a semiconductor wafer including active areas defining a topology; and

disposing a spacer layer on one side of the semiconductor wafer.

26. The method of claim 25, wherein the semiconductor wafer includes the active areas defining a topology on the one side and disposing a spacer layer, comprises:

disposing the spacer layer over the active areas defining a topology.

27. The method of claim 25, wherein disposing a spacer layer, comprises:

disposing the spacer layer over the back side of the semiconductor wafer.

28. The method of claim 25, wherein disposing a spacer layer, comprises:

disposing a solid piece of material on the semiconductor wafer.

29. The method of claim 25, wherein disposing a spacer layer, comprises:

attaching a solid piece of material via one of an adhesive, solder, and anodic bonding.

30. The method of claim 25, wherein disposing a spacer layer, comprises:

disposing a fluid on the semiconductor wafer.

31. The method of claim 25, wherein disposing a spacer layer, comprises:

disposing a fluid on the semiconductor wafer via one of immersion dipping, spraying, and spin coating.

32. The method of claim 25, comprising:

patterning the spacer layer.

33. The method of claim 25, comprising:

patterning the spacer layer via one of photolithographic processing and etching, and photoablation.

34. The method of claim 25, comprising:

patterning the spacer layer via a mechanical treatment.

35. The method of claim 25, comprising:

patterning the spacer layer via one of sawing, milling, grinding, punching, molding, casting, and drilling.

36. A method of providing spacers in stacked die packages, comprising:

providing semiconductor dice in a semiconductor wafer including active areas;

disposing a spacer layer on one side of the semiconductor wafer; and

patterning the spacer layer on the semiconductor wafer.

37. The method of claim 36, comprising:

singulating the spacer layer into singulated spacers.

38. The method of claim 37, wherein the semiconductor dice are integrated circuits and comprising:

singulating the semiconductor wafer into singulated integrated circuit die.