Wafer level stacked package having via contact in encapsulation portion and manufacturing method thereof

• US 20090014876A1
• Filed: 06/30/2008
• Published: 01/15/2009
• Est. Priority Date: 07/13/2007
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Jong-ho, Youn, Cheul-joong, Kim, Young-Lyong, Ahn, Eun-chul
• Application Number:
  US12/216,095
• Publication Number:
  US 20090014876A1
• Time in Patent Office: Days
• US Class Current: 257/738
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73209 Bump and HDI connectors
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/76155 Jetting means, e.g. ink jet
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/82005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/82039 using a laser
• CPC Class Codes: H01L 2224/82102 using jetting, e.g. ink jet
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06548 : Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06565 : the devices having the same size and there being no auxiliary carrier between the devices
• CPC Class Codes: H01L 2225/06582 : Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 2225/1035 : the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3185 : the coating covering also the sidewalls of the semiconductor body
• CPC Class Codes: H01L 24/18 : High density interconnect [HDI] connectors; Manufacturing methods related thereto interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

Provided are a wafer level stacked package with a via contact in an encapsulation portion, and a manufacturing method thereof. A plurality of semiconductor chips and encapsulation portions may be vertically deposited and electrically connected through a via contact that may be vertically formed in the encapsulation portion. Thus, an effective fan-out structure may be produced, vertical deposition may be available regardless of the type of a semiconductor device, and productivity may be improved.

Claims

1. A wafer level stacked package with a via contact in an encapsulation portion, the wafer level stacked package comprising:

a first semiconductor chip with an active region facing upward;

a first encapsulation portion formed along an edge of the first semiconductor chip;

a first wiring pattern connected to bond pads of the first semiconductor chip, the first wiring pattern formed above the first semiconductor chip and extending above the first encapsulation portion;

a second semiconductor chip mounted on the first semiconductor chip using an adhesive member, with an active region of the second semiconductor chip facing upward;

a second encapsulation portion formed along an edge of the second semiconductor chip, the second encapsulation portion located above the first encapsulation portion;

a second wiring pattern connected to bond pads of the second semiconductor chip, the second wiring pattern formed above the second semiconductor chip and extending above the second encapsulation portion; and

a via contact connecting the first wiring pattern and the second wiring pattern, the via contact formed in the second encapsulation portion.

2. The wafer level stacked package of claim 1, wherein the height of the first encapsulation portion is substantially the same as that of the first semiconductor chip.

3. The wafer level stacked package of claim 1, further comprising protruding connection terminals attached to the second wiring pattern.

4. The wafer level stacked package of claim 3, wherein the protruding connection terminals are one of a solder ball and a bump.

5. The wafer level stacked package of claim 1, further comprising one or more additional semiconductor chips located along the same horizontal plane as the first semiconductor chip.

6. The wafer level stacked package of claim 1, further comprising a protective layer formed on bottom surfaces of the first semiconductor chip and the first encapsulation portion.

7. The wafer level stacked package of claim 6, wherein the protective layer is formed of the same material as that of the first encapsulation portion.

8. The wafer level stacked package of claim 6, wherein the protective layer is formed of a material exhibiting a superior heat transfer characteristic as compared to the first encapsulation portion.

9. The wafer level stacked package of claim 1, further comprising one or more additional semiconductor chips, one or more additional encapsulation portions, and one or more additional wiring patterns that are connected through the via contact.

10. The wafer level stacked package of claim 9, wherein the sizes of the first semiconductor chip, the second semiconductor chip, and the one or more additional semiconductor chips are different from one another.

11. The wafer level stacked package of claim 9, wherein the thicknesses of the first semiconductor chip, the second semiconductor chip, and the one or more additional semiconductor chips are different from one another.

12. The wafer level stacked package of claim 10, wherein the via contact connecting the first wiring pattern, the second wiring pattern, and the one or more additional wiring patterns are connected through a plurality of paths.

13. A wafer level stacked package with a via contact in an encapsulation portion, the wafer level stacked package comprising:

a first semiconductor chip with an active region facing upward;

a first encapsulation portion formed along an edge of the first semiconductor chip;

a first wiring pattern connected to bond pads of the first semiconductor chip, the first wiring pattern formed above the first semiconductor chip and extending above the first encapsulation portion;

a second semiconductor chip electrically connected to the first semiconductor chip via a bump, the second semiconductor chip having a size smaller than the first semiconductor chip;

a second encapsulation portion formed along an edge of the second semiconductor chip;

a third semiconductor chip mounted above the second semiconductor chip such that an active region of the third semiconductor chip faces upward;

a third encapsulation portion formed along an edge of the third semiconductor chip above the second encapsulation portion;

a third wiring pattern connected to bond pads of the second semiconductor chip, the third wiring pattern formed above the third semiconductor chip and extending above the third encapsulation portion; and

a via contact connecting the first wiring pattern and the third wiring pattern, the via contact formed in the second and third encapsulation portions.

14. The wafer level stacked package of claim 13, further comprising protruding connection terminals attached to the third wiring pattern.

15. The wafer level stacked package of claim 13, further comprising a protective layer formed on bottom surfaces of the first semiconductor chip and the first encapsulation portion.

39. The wafer level stacked package of claim 13, wherein the third semiconductor chip is mounted directly on the second semiconductor chip using an adhesive member.

16. A method of manufacturing a wafer level stacked package with a via contact in an encapsulation portion, the method comprising:

mounting a plurality of first semiconductor chips on a carrier using an adhesive force such that an active region of the first semiconductor chip faces upward;

forming a first encapsulation portion having the same height as that of the first semiconductor chip on the carrier;

forming a first wiring pattern connected to bond pads of the first semiconductor chip, the first wiring pattern extending above the first encapsulation portion;

mounting a second semiconductor chip on the first semiconductor chip and the first wiring pattern, using an adhesive member, such that an active region of the second semiconductor chip faces upward;

forming a second encapsulation portion having the same height as that of the second semiconductor chip on the first encapsulation portion;

forming a via contact by forming a contact hole that exposes the first wiring pattern in the second encapsulation portion and filling the contact hole with a conductive material; and

forming a second wiring pattern connected to bond pads of the second semiconductor chip, the second wiring pattern extending above the second encapsulation portion and electrically connected to the via contact.

17. The method of claim 16, wherein the first and second encapsulation portions are formed by a method selected from molding, printing, spin coating, and jetting methods.

18. The method of claim 16, wherein the contact hole is formed using a laser drilling method.

19. The method of claim 16, further comprising removing the carrier from the wafer level stacked package.

20. The method of claim 16, wherein the carrier is formed of a material exhibiting a superior heat transfer characteristic as compared to the material of the first encapsulation portion.

21. The method of claim 16, further comprising attaching the protruding connection terminals to the second wiring pattern.

22. The method of claim 16, further comprising forming another semiconductor chip, another encapsulation portion, and another wiring pattern between the first and second semiconductor chips.

23. The method of claim 22, wherein the sizes of the first semiconductor chip, the second semiconductor chip, and the other semiconductor chip are different from one another.

24. The method of claim 22, wherein the thicknesses of the first semiconductor chip, the second semiconductor chip, and the other semiconductor chip are different from one another.

25. The method of claim 22, wherein the via contact connects the first wiring pattern, the other wiring pattern, and the second wiring pattern using one or more paths.

26. The method of claim 16, further comprising one or more additional semiconductor chips, in the same horizontal plane as the first semiconductor chip, are connected to the second semiconductor chip.

27. The method of claim 22, wherein the via contact is formed using a one-time contact hole forming process after the second encapsulation portion is formed.

28. The method of claim 22, wherein a separate via contact is formed after another encapsulation portion is formed on the first encapsulation portion, and the via contact is formed after the second encapsulation portion is formed.

29. The method of claim 21, further comprising separating a wafer level stacked package through a singulation process.

30. The method of claim 16, further comprising forming a protective layer on bottom surfaces of the first semiconductor chip and the first encapsulation portion.

31. The method of claim 30, wherein the protective layer is formed of a material exhibiting a superior heat transfer characteristic as compared to the material of the first encapsulation portion.

32. A method of manufacturing a wafer level stacked package with a via contact in an encapsulation portion, the method comprising:

mounting a first semiconductor chip on a carrier such that an active region of the first semiconductor chip faces downward;

forming a first encapsulation portion completely covering the first semiconductor chip on the carrier;

removing the carrier and arranging the active region of the first semiconductor chip to face upward;

forming a first wiring pattern connected to bond pads of the first semiconductor chip and extending above the first encapsulation portion;

mounting a second semiconductor chip on the first semiconductor chip and the first wiring pattern, using an adhesive member, such that an active region of the second semiconductor chip faces upward;

forming a second encapsulation portion having the same height as that of the second semiconductor chip on the first encapsulation portion;

forming a via contact by forming a contact hole that exposes the first wiring pattern in the second encapsulation portion and filling the contact hole with a conductive material; and

forming a second wiring pattern connected to bond pads of the second semiconductor chip, the second wiring pattern extending above the second encapsulation portion and electrically connected to the via contact.

33. The method of claim 32, further comprising attaching protruding connection terminals to the second wiring pattern.

34. The method of claim 32, further comprising forming another semiconductor chip, another encapsulation portion, and another wiring pattern between the first and second semiconductor chips.

35. The method of claim 33, further comprising separating a wafer level stacked package using a singulation process.

36. A method of manufacturing a wafer level stacked package with a via contact in an encapsulation portion, the method comprising:

mounting a plurality of first semiconductor chips on a carrier such that an active region of the first semiconductor chip faces upward, the first semiconductor having a plurality of bond pads;

forming a first encapsulation portion having the same height as that of the first semiconductor chip on the carrier;

forming a first wiring pattern connected to one or more of the plurality of bond pads of the first semiconductor chip, the first wiring pattern extending above the first encapsulation portion;

mounting a second semiconductor chip above the first semiconductor chip, the second semiconductor having a size smaller than that of the first semiconductor chip, the second semiconductor connected one or more of the bond pads of the first semiconductor chip that are not connected to the first wiring pattern;

forming a second encapsulation portion having the same height as that of the second semiconductor chip, the second encapsulation portion located above the first encapsulation portion;

mounting a third semiconductor chip above the second semiconductor chip, such that an active region of the third semiconductor chip faces upward;

forming a third encapsulation portion having the same height as that of the third semiconductor chip, the second encapsulation portion located above the second encapsulation portion;

forming a via contact by forming a contact hole that exposes the first wiring pattern in the second and third encapsulation portions and filling the contact hole with a conductive material; and

forming a third wiring pattern connected to bond pads of the third semiconductor chip, the third wiring pattern extending above the third encapsulation portion and electrically connected to the via contact.

37. The method of claim 36, further comprising forming protruding connection terminals attached to the third wiring pattern.

38. The method of claim 37, further comprising separating a wafer level stacked package through a singulation process.