DYNAMIC RANDOM ACCESS MEMORY WITH AN ELECTROSTATIC DISCHARGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

• US 20090014886A1
• Filed: 12/05/2007
• Published: 01/15/2009
• Est. Priority Date: 07/11/2007
• Status: Active Grant

• Current Assignee: Nanya Technology Corporation
• Original Assignee: Nanya Technology Corporation
• Inventors: Chiu, Shih-Yang, Hsiao, Ching-Nan, Huang, Chung-Lin, Chuang, Ying-Cheng
• Granted Patent: US 7,714,445 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells

Abstract

The invention provides a dynamic random access memory (DRAM) with an electrostatic discharge (ESD) region. The upper portion of the ESD plug is metal, and the lower portion of the ESD plug is polysilicon. This structure may improve the mechanical strength of the ESD region and enhance thermal conductivity from electrostatic discharging. In addition, the contact area between the ESD plugs and the substrate can be reduced without increasing aspect ratio of the ESD plugs. The described structure is completed by a low critical dimension controlled patterned photoresist, such that the processes and equipments are substantially maintained without changing by a wide margin.

Claims

1. A method for manufacturing an electrostatic discharge structure, comprising the steps of:

providing a substrate having an electrostatic discharge region, wherein the electrostatic discharge region has a plurality of conductive structures;

forming an interlayer dielectric layer on top of the substrate;

forming a contact hole in the interlayer dielectric layer to exposes part of the substrate, wherein the contact hole is formed between each two of the conductive structures; and

forming a conductor in the contact hole and on the top surface of the interlayer dielectric layer, wherein the conductor electrically connects to the substrate.

2. The method as claimed in claim 1, wherein the contact hole forming step comprises:

forming a sacrificial layer on the substrate and between every two adjacent conductive structures;

forming the interlayer dielectric layer on top of the substrate and exposing a top surface of the sacrificial layer; and

removing the sacrificial layer to form the contact hole.

3. The method as claimed in claim 2 further comprising forming a collar insulator on a sidewall of the contact hole.

4. The method as claimed in claim 1, wherein each of the conductive structures comprises a gate dielectric layer, a metal silicide layer, a polysilicon layer, and a hard mask layer sequentially stacked on the substrate.

5. The method as claimed in claim 2 further comprising forming an insulating liner sandwiched between the conductor and the substrate, wherein the insulating liner has an opening for a connection of the conductor to the substrate.

6. The method as claimed in claim 3 further comprising forming an insulating liner sandwiched between the conductor and the substrate, wherein the insulating liner has an opening for a connection of the conductor to the substrate.

7. An electrostatic discharge structure, comprising:

a substrate having a plurality of conductive structures thereon;

an interlayer dielectric layer formed on the substrate, wherein the interlayer dielectric layer has a contact hole between the conductive structures to expose part of the substrate;

a sacrificial layer formed in a lower portion of the contact hole; and

a conductor in an upper portion of the contact hole and overlying the top surface of the interlayer dielectric layer.

8. The electrostatic discharge structure as claimed in claim 7, further comprising an insulating liner sandwiched between the conductor and the substrate, wherein the insulating liner has an opening for a connection of the conductor to the substrate.

9. The electrostatic discharge structure as claimed in claim 8 further comprising a collar insulator formed on an inner surface of the contact hole.