Method and Apparatus for Packaging an Integrated Chip and Antenna

• US 20090015485A1
• Filed: 05/30/2008
• Published: 01/15/2009
• Est. Priority Date: 07/13/2007
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Floyd, Brian Allan, Morton, Robert M., Liu, Duixian
• Granted Patent: US 8,018,384 B2
• Time in Patent Office: Days
• US Class Current: 343/700.MS
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/16195 Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01Q 21/0006 Particular feeding systems
• CPC Class Codes: H01Q 21/065 Patch antenna array
• CPC Class Codes: H01Q 9/0457 electromagnetically coupled to the feed line
• CPC Class Codes: Y10T 29/49016 Antenna or wave energy "plumbing" making

Abstract

In an illustrative embodiment, an apparatus includes at least one antenna structure located on a first surface of a first substrate; at least one pad located on the first surface of the first substrate; and at least one via traversing the first substrate and thereby connecting the at least one pad located on the first surface of the first substrate to at least one pad located on a second surface. The at least one pad located on the first surface of the first substrate is operatively coupleable to at least one pad located on a surface of an integrated circuit and the at least one pad located on the second surface is operatively coupleable to at least one pad located on a surface of a printed circuit board. The at least one via is thereby operative to couple the at least one pad located on the surface of the integrated circuit and the at least one pad located on the surface of the printed circuit board.

Claims

1. An apparatus comprising:

at least one antenna structure located on a first surface of a first substrate;

at least one pad located on the first surface of the first substrate; and

at least one via traversing the first substrate and thereby connecting the at least one pad located on the first surface of the first substrate to at least one pad located on a second surface;

wherein the at least one pad located on the first surface of the first substrate is operatively coupleable to at least one pad located on a surface of an integrated circuit;

the at least one pad located on the second surface is operatively coupleable to at least one pad located on a surface of a printed circuit board; and

the at least one via is thereby operative to couple the at least one pad located on the surface of the integrated circuit and the at least one pad located on the surface of the printed circuit board.

2. The apparatus of claim 1, wherein the first surface is capable of having the integrated circuit flip-chip mounted thereto.

3. The apparatus of claim 1, wherein the second surface is capable of having the printed circuit board flip-chip mounted thereto.

4. The apparatus of claim 1, wherein the antenna structure comprises at least one feed line operatively coupled to the at least one pad located on the first surface.

5. The apparatus of claim 1, wherein the first substrate is a low-loss substrate.

6. The apparatus of claim 1, wherein the second surface is a surface of the first substrate.

7. The apparatus of claim 1, wherein the second surface is a surface of a second substrate and wherein the at least one via traverses the first and second substrates.

8. The apparatus of claim 7, wherein the second substrate has a cavity located between at least a portion of the at least one antenna and at least a portion of a ground plane located proximate to the second surface.

9. The apparatus of claim 8, wherein the surfaces of the second substrate adjacent to the cavity are plated with metal.

10. The apparatus of claim 8, wherein a ground plane is formed on the surface of the printed circuit board.

11. The apparatus of claim 7, further comprising a third substrate formed between the first and second substrates;

wherein the at least one via traverses the first, second and third substrates;

wherein the third substrate has a cavity located between at least a portion of the at least one antenna.

12. The apparatus of claim 11, wherein the surfaces of the second and third substrates adjacent to the cavity are plated with metal.

13. The apparatus of claim 11, wherein the surface of the third substrate adjacent to the cavity provides a ground plane.

14. An apparatus comprising:

a plurality of pads located on a surface of a substrate opposite a printed circuit board;

at least one integrated circuit operatively coupled to at least a portion of the plurality of pads and located proximate to the surface of the substrate opposite the printed circuit board;

a plurality of antennas located proximate to the surface of the substrate opposite the printed circuit board; and

at least one feed line operatively connected between each of the plurality of antennas and a given one or more of the plurality of pads.

15. The apparatus of claim 14, further comprising:

at least one pad proximate to a surface of the printed circuit board and located between the substrate and the printed circuit board; and

at least one via traversing the substrate, wherein each via connects a given one of the plurality of pads located between the integrated circuit and the substrate with the at least one pad located proximate to the surface of the printed circuit board.

16. A method of packaging an antenna, comprising the steps of:

forming an antenna on a first surface of a first substrate;

flip-chip mounting an integrated circuit to the first surface of the first substrate; and

flip-chip mounting a second surface opposite the first surface of the first substrate to a printed circuit board.

17. The method of claim 16, further comprising the step of forming at least one via traversing the first substrate, the at least one via operatively coupling at least one pad located on the first surface to the at least one via connecting the at least one pad located on the second surface.

18. The method of claim 17, wherein the at least one via operatively couples at least one pad located on a surface of the integrated circuit adjacent to the first surface to at least one pad located on a surface of the printed circuit board adjacent to the second surface.

19. The method of claim 16, wherein the second surface is a surface of the first substrate.

20. The method of claim 16, wherein the second surface is a surface of a second substrate.