DATA PROCESSOR AND GRAPHIC DATA PROCESSING DEVICE

• US 20090015590A1
• Filed: 09/24/2008
• Published: 01/15/2009
• Est. Priority Date: 08/07/2003
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: HARA, HIROTAKA, Hirade, Kazuhiro, Takano, Makoto, Saeki, Mitsuhiro, Hamasaki, Hiroyuki
• Granted Patent: US 7,868,892 B2
• Time in Patent Office: Days
• US Class Current: 345/522
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 11/203 Drawing of straight lines or curves

Abstract

An object of the present invention is to improve efficiency of transfer of control information, graphic data, and the like for drawing and display control in a graphic data processor. A graphic data processor includes: a CPU; a first bus coupled to the CPU; a DMAC for controlling a data transfer using the first bus; a bus bridge circuit for transmitting/receiving data to/from the first bus; a three-dimensional graphics module for receiving a command from the CPU via the first bus and performing a three-dimensional graphic process; a second bus coupled to the bus bridge circuit and a plurality of first circuit modules; a third bus coupled to the bus bridge circuit and second circuit modules; and a memory interface circuit coupled to the first and second buses and the three-dimensional graphic module and connectable to an external memory, wherein the bus bridge circuit can control a direct memory access transfer between an external circuit and the second bus.

Claims

1-12. -12. (canceled)

13. A graphic data processor formed on a semiconductor chip, comprising:

a central processor;

a first bus coupled to said central processor;

a direct memory access controller for controlling data transfer using said first bus;

a bus bridge device for transmitting/receiving data to/from said first bus;

a three-dimensional graphics device coupled to the first bus for receiving a command from said central processor via said first bus and performing a three-dimensional graphic process;

a second bus coupled to said bus bridge device and a plurality of first circuit devices;

a third bus coupled to said three-dimensional graphics device;

a fourth bus which is coupled to said bus bridge device and is capable of being used for register setting from said central processor to the plurality of first circuit devices; and

memory interface means coupled to said first bus, said second bus, and said three-dimensional graphics device via said third bus directly, and capable of being coupled to a memory,

wherein said bus bridge device is capable of controlling a direct memory access transfer between a device coupled to the outside of the semiconductor chip and said second bus,

wherein said memory interface means arbitrates access between said memory and said central processor for transferring data to/from said memory, between said memory and said three-dimensional graphics device for receiving data from said memory via said third bus independently from said first bus and said second bus, and between said memory and one of said first circuit devices for receiving data from said memory via said second bus independently from said first bus and said third bus, and

wherein said three-dimensional graphics device receives graphics data via said third bus.

14. The graphic data processor according to claim 13,

wherein said bus bridge device is also configured to execute a data transfer between said second and fourth buses,

wherein the memory interface means arbitrates access among said first bus, said second bus, and said fourth bus to said memory using a multi-level arbitration algorithm, and

wherein the memory interface means arbitrates access among said plurality of first devices to said second bus and among said plurality of second circuit devices to said fourth bus.

15. The graphic data processor according to claim 13, wherein said central processor has a super scalar configuration for executing two commands in one cycle, wherein two sets of data of a predetermined number of bits are prepared in a processing cycle of said central processor, and wherein the prepared two sets of data can be transferred to the first bus in one bus cycle.

16. The graphic data processor according to claim 13, further comprising:

a plurality of second circuit devices including a GPS device coupled to said fourth bus,

wherein said plurality of first circuit devices comprises a two-dimensional graphics device, and a display controller for performing display control on graphic data generated by said two-dimensional or three-dimensional graphics device.

17. The graphic data processor according to claim 16, wherein at the time of drawing a thick line, said two-dimensional graphics device obtains a drawing line width specifying vector for specifying drawing line width in a direction perpendicular to a center line specifying a drawing direction, obtains a rectangle of a thick line based on a start point and an end point of the center line and said drawing line width specifying vector, obtains drawing coordinates of four vertexes corresponding to pixels by performing a rounding process on logic coordinates of the four vertexes of the rectangle, and draws a region surrounded by the drawing coordinates of the four vertexes as a polygon, and

wherein said two-dimensional graphics device obtains a drawing line width specifying vector so that right and left parts of the vector become asymmetrical with respect to the center line in the drawing direction.