DYNAMIC VOLTAGE ADJUSTMENT FOR MEMORY
First Claim
1. A method of powering a memory comprising:
- operating a memory of an integrated circuit, the operating a memory includes powering the memory at a supply voltage;
testing a test memory of the integrated circuit concurrently while operating the memory, the test memory and the memory each including bit cells of a first bit cell configuration type; and
adjusting a voltage level of the supply voltage, while operating the memory, based on the testing the test memory.
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Accused Products
Abstract
A power supply voltage for a memory on an integrated circuit is dynamically adjusted during the operating of the memory. The operating of the memory includes powering the memory at a supply voltage. A test memory of the integrated circuit is concurrently powered while operating the memory. The test memory and the memory each include bit cells of a first bit cell configuration type. A voltage level of the supply voltage is adjusted, while operating the memory, based on the testing of the test memory. The voltage level is adjusted with external variations to assume a value that guarantees no failed operation of the memory but also accurately minimizes the supply voltage. The system and method may be implemented with any type of memory. The memory and test memory may be physically implemented either separated or interspersed on the integrated circuit.
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Citations
21 Claims
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1. A method of powering a memory comprising:
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operating a memory of an integrated circuit, the operating a memory includes powering the memory at a supply voltage; testing a test memory of the integrated circuit concurrently while operating the memory, the test memory and the memory each including bit cells of a first bit cell configuration type; and adjusting a voltage level of the supply voltage, while operating the memory, based on the testing the test memory. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method of powering a memory, comprising:
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powering a memory of an integrated circuit at an operating voltage level; testing for a first time, a test memory of the integrated circuit; adjusting the operating voltage level to a first adjusted operating voltage level based on the testing for the first time; powering the memory at the first adjusted operating voltage level after the adjusting for a first time; testing for a second time, the test memory; adjusting the first adjusted operating voltage level to a second adjusted operating voltage level based on the testing for a second time; and powering the memory at the second adjusted operating voltage level after the adjusting the first adjusted operating voltage level. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A system comprising:
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a memory of an integrated circuit, the memory including a supply terminal for receiving an operating supply voltage; a test memory of the integrated circuit, the test memory including a test supply terminal for receiving a test supply voltage for powering the test memory, the test memory and the memory each including bit cells of a first bit cell configuration type; and test circuitry coupled to the test memory for testing and determining performance of the test memory, the test circuitry operable for finding a lowest test supply voltage level received at the test supply terminal at which the test memory passes testing; wherein the supply terminal of the memory is configured to receive the operating supply voltage that is adjustable during memory operation based on performance of the test memory as determined by the test circuitry. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21)
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Specification