MANUFACTURING PROCESS FOR INTEGRATED MICROELECTROMECHANICAL COMPONENTS

• US 20090017305A1
• Filed: 07/28/2008
• Published: 01/15/2009
• Est. Priority Date: 01/26/2006
• Status: Abandoned Application

• Current Assignee: Telefunken Semiconductors GmbH & Co. KG.
• Original Assignee: Telefunken Semiconductors GmbH & Co. KG.
• Inventors: Wuertz, Alida, Dietz, Franz
• Application Number:
  US12/181,299
• Publication Number:
  US 20090017305A1
• Time in Patent Office: Days
• US Class Current: 428/409
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: Y10T 428/31 Surface property or characteristic of web, sheet or block

Abstract

A method for producing integrated microelectromechanical components is provided, whereby a first conductive layer is produced on a first insulating layer, the first conductive layer is structured, a second insulating layer is produced, a second conductive layer is produced, at least one etch opening is produced for at least partial etching of the second insulating layer beneath the second conductive layer in order to produce at least one hollow space, and at least a part of the first conductive layer and the second conductive layer is electrically contacted.

Claims

1. A method for producing integrated microelectromechanical components, the method comprising:

providing a first conductive layer on a first insulating layer;

structuring the first conductive layer;

providing a second insulating layer;

providing a second conductive layer;

providing at least one etch opening for at least partial etching of the second insulating layer beneath the second conductive layer in order to produce at least one hollow space; and

electrically contacting at least a portion of the first conductive layer and the second conductive layer.

2. The method according to claim 1, wherein the at least one etch opening is produced in the second conductive layer.

3. The method according to claim 1, wherein the at least partial etching of the second insulating layer under the second conductive layer takes place after the electrical contacting of the first and second conductive layers.

4. The method according to claim 1, wherein the at least one etch opening is closed.

5. The method according to claim 1, wherein the first insulating layer is produced on a substrate layer.

6. The method according to claim 1, wherein the structuring of the first conductive layer takes place in multiple, staggered, steps.

7. The method according to claim 1, wherein the structuring of the first conductive layer involves subregions of this layer in the full thickness thereof to the first insulating layer.

8. The method according to claim 1, wherein a highly doped material is used as the starting material for the first conductive layer.

9. The method according to claim 1, wherein metal is used as the starting material for the first conductive layer.

10. The method according to claim 1, wherein a doping of the first conductive layer takes place after the application on the first insulating layer in another process step.

11. The method according to claim 1, wherein a doping of the first conductive layer takes place after the structuring of the layer.

12. The method according to claim 1, wherein the surface of the second insulating layer is leveled after the deposition process.

13. The method according to claim 1, wherein prior to deposition of the second conductive layer, an insulating layer is deposited that extends over the second conductive layer at least in subregions.

14. The method according to claim 13, wherein an etch opening is produced by the etching of the insulating layer present in the subregions.

15. The method according to claim 1, wherein, after the production of a hollow space in the second insulating layer, a complete or partial passivation of the hollow space takes place by introduction of a gas or liquid through etch openings.

16. The method according to claim 15, wherein a defined internal pressure is produced in the hollow spaces during sealing of the etch openings.

17. The method according to claim 1, wherein additional material is deposited on the second conductive layer at a later time.

18. A microelectromechanical component comprising:

at least two insulating layers;

at least two conductive layers, wherein a conductive layer is located on an insulating layer; and

at least one membrane being provided over at least one hollow space, the hollow space being provided at least partially in the second insulating layer.

19. The microelectromechanical component according to claim 18, wherein the electrical contacting of the two conductive layers takes place from one side.

20. The microelectromechanical component according to claim 18, wherein connections to connect multiple microelectromechanical components into an array are provided in the conductive layers.