INTEGRATED CIRCUIT, MEMORY MODULE AND SYSTEM

• US 20090019195A1
• Filed: 07/13/2007
• Published: 01/15/2009
• Est. Priority Date: 07/13/2007
• Status: Abandoned Application

• Current Assignee: Qimonda AG (Infineon Technologies AG)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: DJORDJEVIC, SRDJAN
• Application Number:
  US11/777,867
• Publication Number:
  US 20090019195A1
• Time in Patent Office: Days
• US Class Current: 710/53
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports

Abstract

An integrated circuit comprises a first data interface configured to be coupled to a first memory device, a second data interface configured to be coupled to a second memory device, a first control interface configured to be coupled to the first memory device, and a second control interface configured to be coupled to the second memory device. The control interfaces are arranged between the first data interface and the second data interface or the data interfaces are arranged between the first control interface and the second control interface.

Claims

1. An integrated circuit, comprising:

a first data interface configured to be coupled to a first memory device;

a second data interface configured to be coupled to a second memory device;

a first control interface configured to be coupled to the first memory device; and

a second control interface configured to be coupled to the second memory device;

wherein the control interfaces are arranged between the first data interface and the second data interface or the data interfaces are arranged between the first control interface and the second control interface.

2. The integrated circuit as claimed in claim 1, further comprising:

a supply voltage interface configured to receive at least one supply voltage; and

a controller interface configured to be coupled to a memory controller.

3. The integrated circuit as claimed in claim 2,

wherein the first data interface, the at least one control interface and the second data interface are arranged in a contiguous interface region, and

wherein the supply voltage interface is arranged between the interface region and the controller interface.

4. The integrated circuit as claimed in claim 1, wherein a region occupied by at least one of the first and second data interface and the first and second control interface is a rectangle or provides any other non-concave contour.

5. The integrated circuit as claimed in claim 1, wherein the first control interface is arranged between the first data interface and the second control interface, and wherein the second control interface is arranged between the first control interface and the second data interface.

6. The integrated circuit as claimed in claim 1, wherein a direction from the first control interface to the second control interface is perpendicular to the direction from the first data interface to the second data interface.

7. The integrated circuit as claimed in claim 1, wherein the integrated circuit is a semiconductor die with an integrated circuit, and wherein at least one of the data and control interfaces comprises electrical contacts at a surface of the die.

8. The integrated circuit as claimed in claim 1, wherein the integrated circuit comprises an integrated circuit in a package, and wherein at least one of the data and control interfaces comprises electrical contacts at a surface of the package.

9. The integrated circuit as claimed in claim 1, wherein the integrated circuit is a memory buffer.

10. An apparatus, comprising:

a memory module; and

an integrated circuit formed on the memory module, the integrated circuit comprising;

a first data interface configured to be coupled to a first memory device;

a second data interface configured to be coupled to a second memory device;

a first control interface configured to be coupled to the first memory device; and

a second control interface configured to be coupled to the second memory device; and

wherein the control interfaces are arranged between the first data interface and the second data interface or the data interfaces are arranged between the first control interface and the second control interface.

11. The apparatus as claimed in claim 10, wherein the memory module further comprises:

a first group of memory devices coupled to the first data interface and to the first control interface; and

a second group of memory devices coupled to the second data interface and to the second control interface.

12. The apparatus as claimed in claim 11, wherein the first group of memory devices is coupled to a memory buffer via a first bus, and wherein the second group of memory modules is coupled to the memory buffer via a second bus.

13. The apparatus as claimed in claim 10, further comprising a register coupled between the first control interface and a first group of memory devices.

14. A system, comprising:

a processor; and

an integrated circuit communicatively connected to the processor, the integrated circuit comprising;

a first data interface configured to be coupled to a first memory device;

a second data interface configured to be coupled to a second memory device;

a first control interface configured to be coupled to the first memory device; and

a second control interface configured to be coupled to the second memory device;

wherein the control interfaces are arranged between the first data interface and the second data interface or the data interfaces are arranged between the first control interface and the second control interface.

15. The system as claimed in claim 14, further comprising:

a first memory device coupled to the first data interface and to the first control interface of the integrated circuit;

a second memory device coupled to the second data interface and to the second control interface of the integrated circuit,

wherein the integrated circuit is a memory buffer.

16. The system as claimed in claim 15, wherein the integrated circuit and the first and second memory devices are arranged at a memory module comprised in the system.

17. The system as claimed in claim 14, the system further comprising:

a memory controller coupled to a controller interface of the integrated circuit.

18. The system as claimed in claim 14, wherein the processor and the integrated circuit are disposed on a printed circuit board, the printed circuit board being a main board for a computer, and wherein the processor is coupled to a controller interface of the integrated circuit.

19. The system as claimed in claim 14, further comprising:

a printed circuit board;

a first memory module slot at the printed circuit board, the first memory module slot being coupled to the first data interface and to the first control interface of the integrated circuit; and

a second memory module slot at the printed circuit board, the second memory module slot being coupled to the second data interface and to the second control interface of the integrated circuit.

20. The system as claimed in claim 19, the system further comprising:

a memory controller coupled to a controller interface of the integrated circuit.