WIRELESSLY CONFIGURABLE MEMORY DEVICE ADDRESSING

• US 20090019250A1
• Filed: 09/23/2008
• Published: 01/15/2009
• Est. Priority Date: 01/31/2007
• Status: Active Grant

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Markison, Timothy W., ROFOUGARAN, AHMADREZA (REZA)
• Granted Patent: US 8,239,650 B2
• Time in Patent Office: Days
• US Class Current: 711/170
• CPC Class Codes: G06F 12/0623 for memory modules
• CPC Class Codes: G06F 12/0646 Configuration or reconfiguration
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory device includes a plurality of memory modules and a memory management module. A memory module of the plurality of memory modules includes a plurality of memory cells and a memory millimeter wave (MMW) transceiver. The memory management module determines a main memory configuration for at least some of the plurality of memory modules. The memory management module also determines physical addresses for the main memory configuration and determines a MMW communication resource table that includes an allocation mapping of one or more MMW communication resources to one or more of the at least some of the plurality of memory modules.

Claims

1. A memory device comprises:

a plurality of memory modules, wherein a memory module of the plurality of memory modules includes a plurality of memory cells and a memory millimeter wave (MMW) transceiver; and

a memory management module coupled to;

determine a main memory configuration for at least some of the plurality of memory modules;

determine addresses of the main memory configuration; and

determine a MMW communication resource table that includes an allocation mapping of one or more MMW communication resources to one or more of the at least some of the plurality of memory modules.

2. The memory device of claim 1, wherein the memory management module further functions to determine the main memory configuration by at least one of:

access a pre-programmed default configuration;

access a look up table to determine the main memory configuration from one of a plurality of configurations; and

determine memory addressability.

3. The memory device of claim 1, wherein the memory management module further functions to determine the main memory configuration by:

at start-up of a device including the memory device;

determine start-up applications requiring access to main memory;

allocate a portion of the plurality of memory modules for the start-up applications;

configure the portion of the plurality of memory modules in accordance with memory requirements of the start-up applications;

during on-going operation of the device including the memory device;

determine active applications requiring access to main memory, wherein the active applications includes at least some of the start-up applications;

allocate the plurality of memory modules for the active applications;

configure the plurality of memory modules in accordance with memory requirements of the active applications.

4. The memory device of claim 1, wherein the memory management module further functions to determine the main memory configuration by:

allocate a first portion of the plurality of memory modules for user applications;

allocate a second portion of the plurality of memory modules for operating system applications; and

allocate a third portion of the plurality of memory modules for direct memory access.

5. The memory device of claim 1, wherein the memory management module further functions to determine the main memory configuration by:

determine memory line size; and

determine the main memory configuration in accordance with the memory line size.

6. The memory device of claim 1, wherein the memory management module comprises:

a memory management unit operable to;

receive a memory access request that includes a logical address;

identify at least one memory module of the at least some of the plurality of memory modules based on the logical address;

determine at least one MMW communication resource for the at least one memory module in accordance with the MMW communication resource table; and

generate a memory module address message based on the memory access request and the identity of the at least one memory module;

a memory MMW transceiver operable to;

convert the memory module address message into a MMW signal in accordance with the at least one MMW communication resource; and

transmit the MMW signal to the at least one memory module via the at least one MMW communication resource.

7. The memory device of claim 6 further comprises:

the memory management module receiving the memory access request from a processing core of a processing module.

8. The memory device of claim 6 further comprises:

the memory MMW transceiver operable to;

receive an inbound MMW memory access signal;

convert the inbound MMW memory access signal into the memory access request; and

convey the memory access request to the memory management unit.

9. A memory device comprises:

a plurality of memory modules, wherein a memory module of the plurality of memory modules includes a plurality of memory cells and a memory millimeter wave (MMW) transceiver; and

a memory management module coupled to;

receive a memory access request that includes a logical address;

determine whether one or more of the plurality of memory modules satisfies the memory access request based on the logical address and a table of logical address to memory modules;

when the one or more of the plurality of memory modules satisfies the memory access request, generate a memory module message identifying the one or more of the plurality of memory modules and at least a portion of the memory access request;

convert the memory module message into a millimeter wave (MMW) memory signal in accordance with a memory module addressing communication resource; and

transmit the MMW memory signal to the one or more memory modules via the memory module addressing communication resource;

wherein;

the one or more memory modules functions to;

receive the MMW memory signal via the memory module addressing communication resource;

recover the memory module message from the MMW memory signal;

process the at least a portion of the memory access request;

generate a memory access response when required;

convert the memory access response into a MMW memory response signal in accordance with a wireless communication resource; and

transmit the MMW memory response signal via the wireless communication resource.

10. The memory device of claim 9, wherein the memory management module determining whether the one or more of the plurality of memory modules satisfies the memory access request further comprises:

determine whether a current entry in the table of logical address to memory modules exists for the logical address; and

when the current entry in the table of logical address to memory modules exists for the logical address, determining that the one or more of the plurality of memory modules satisfies the memory access request.

11. The memory device of claim 10 further comprises the memory management module operable to:

when the current entry in the table of logical address to memory modules does not exist for the logical address, generate a swap message;

convert the swap message into a MMW swap message in accordance with a swap memory wireless communication resource;

transmit the MMW swap message via the swap memory wireless communication resource to the plurality of memory modules and to a secondary memory module.

12. The memory device of claim 11 further comprises:

an addressed one or more memory modules of the plurality of memory modules operable to;

convert the MMW swap message into the swap message;

process the swap message to retrieve data stored within the addressed one or more memory modules;

convert the retrieved data into a MMW data signal;

transmit the MMW data signal to the secondary memory module; and

the secondary memory module operable to;

receive the MMW data signal;

recapture the retrieved data from the MMW data signal; and

store the retrieved data at a designated location.

13. The memory device of claim 12 further comprises:

the secondary memory module operable to;

convert the MMW swap message into the swap message;

process the swap message to retrieve second data stored within a second designated location to produce second retrieved data;

convert the second retrieved data into a second MMW data signal;

transmit the second MMW data signal to the addressed one or more memory modules; and

the addressed one or more memory modules operable to;

receive the second MMW data signal;

recapture the second retrieved data from the second MMW data signal; and

store the second retrieved data.

14. The memory device of claim 9, wherein the memory management module generating the memory module message further comprises:

interpret the memory access request to identify a page of memory based on the logical address;

determine whether the page is stored in the one of the plurality of memory modules or in the one and at least one other memory module of the plurality of memory modules;

when the page is stored in the one of the plurality of memory modules, determine whether at least part of another page is stored in the one of the plurality of memory modules;

when the at least part of another page is not stored in the one of the plurality of memory modules, generate the memory module message to include an identification code of the one of the plurality of memory modules; and

when at least part of another page is stored in the one of the plurality of memory modules, generate the memory module message to include the identification code of the one of the plurality of memory modules and a local address.

15. The memory device of claim 14, wherein the memory management module generating the memory module message further comprises:

when the page is stored in the one and at least one other memory module of the plurality of memory modules, determine whether at least part of another page is stored in the one or the at least one other memory module of the plurality of memory modules;

when the at least part of another page is not stored in the one or the at least one other memory module of the plurality of memory modules, generate the memory module message to include an identification code of the one and of the at least one other memory module of the plurality of memory modules; and

when at least part of another page is stored in the one or the at least one other memory module of the plurality of memory modules, generate the memory module message to include the identification code of the one of the plurality of memory modules and a first corresponding local address and the identification code of the at least one other memory module of the plurality of memory modules and a second corresponding local address.

16. A circuit comprises:

a processing module that includes;

a processing core operable to produce a memory access request;

processing core cache coupled to the processing core; and

a millimeter wave (MMW) transceiver coupled to the processing core cache;

a configurable memory that includes a plurality of memory modules, wherein a memory module of the plurality of memory modules includes a plurality of memory cells and a memory MMW transceiver; and

a memory management unit operable to;

receive the memory access request;

interpret the memory access request to determine whether one or more of the plurality of memory modules satisfies the memory access request;

when the one or more of the plurality of memory modules satisfies the memory access request, generate a memory module message that includes identity of the one or more of the plurality of memory modules and at least a portion of the memory access request;

convert the memory module message into a MMW memory access signal; and

transmit the MMW memory access signal, wherein;

the one or more memory modules functions to;

receive the MMW memory access signal;

recover the memory module message from the MMW memory signal;

process the at least a portion of the memory access request.

17. The circuit of claim 16, wherein the one or more memory modules further functions to, when the memory access request is a read command:

generate a memory access response;

convert the memory access response into a MMW memory response signal; and

transmit the MMW memory response signal.

18. The circuit of claim 16, wherein the memory management module further functions to interpret the memory access request to determine whether one or more of the plurality of memory modules satisfies the memory access request by:

retrieving a logical address from the memory access request;

determining whether a current entry in a table of logical address to memory modules exists for the logical address; and

when the current entry in the table of logical address to memory modules exists for the logical address, determining that the one or more of the plurality of memory modules satisfies the memory access request.

19. The circuit of claim 18 further comprises the memory management module operable to:

when the current entry in the table of logical address to memory modules does not exist for the logical address, generate a swap message;

convert the swap message into a MMW swap message;

transmit the MMW swap message to the plurality of memory modules and to a secondary memory.

20. The circuit of claim 19 further comprises:

an addressed one or more memory modules of the plurality of memory modules operable to;

convert the MMW swap message into the swap message;

process the swap message to retrieve data stored within the addressed one or more memory modules;

convert the retrieved data into a MMW data signal;

transmit the MMW data signal to the secondary memory; and

the secondary memory operable to;

receive the MMW data signal;

recapture the retrieved data from the MMW data signal; and

store the retrieved data at a designated location.

21. The circuit of claim 20 further comprises:

the secondary memory operable to;

convert the MMW swap message into the swap message;

process the swap message to retrieve second data stored within a second designated location to produce second retrieved data;

convert the second retrieved data into a second MMW data signal;

transmit the second MMW data signal to the addressed one or more memory modules; and

the addressed one or more memory modules operable to;

receive the second MMW data signal;

recapture the second retrieved data from the second MMW data signal; and

store the second retrieved data.

22. The circuit of claim 16, wherein the memory management module generating the memory module message further comprises:

interpret the memory access request to identify a page of memory to retrieve based on a logical address;

determine whether the page is stored in the one of the plurality of memory modules or in the one and at least one other memory module of the plurality of memory modules;

when the page is stored in the one of the plurality of memory modules, determine whether at least part of another page is stored in the one of the plurality of memory modules;

when the at least part of another page is not stored in the one of the plurality of memory modules, generate the memory module message to include an identification code of the one of the plurality of memory modules; and

when at least part of another page is stored in the one of the plurality of memory modules, generate the memory module message to include the identification code of the one of the plurality of memory modules and a local address.

23. The circuit of claim 22, wherein the memory management module generating the memory module message further comprises:

when the page is stored in the one and at least one other memory module of the plurality of memory modules, determine whether at least part of another page is stored in the one or the at least one other memory module of the plurality of memory modules;

when the at least part of another page is not stored in the one or the at least one other memory module of the plurality of memory modules, generate the memory module message to include an identification code of the one and of the at least one other memory module of the plurality of memory modules; and

when at least part of another page is stored in the one or the at least one other memory module of the plurality of memory modules, generate the memory module message to include the identification code of the one of the plurality of memory modules and a first corresponding local address and the identification code of the at least one other memory module of the plurality of memory modules and a second corresponding local address.