Protecting tag information in a multi-level cache hierarchy

• US 20090019306A1
• Filed: 07/11/2007
• Published: 01/15/2009
• Est. Priority Date: 07/11/2007
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Narayanan, Rajagopal K., Hum, Herbert
• Application Number:
  US11/827,197
• Publication Number:
  US 20090019306A1
• Time in Patent Office: Days
• US Class Current: 714/2
• CPC Class Codes: G06F 11/1064 in cache or content addressable memories
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In one embodiment, the present invention includes a shared cache memory that is inclusive with other cache memories coupled to it. The shared cache memory includes error correction logic to correct an error present in a tag array of one of the other cache memories and to provide corrected tag information to replace a tag entry in the tag array including the error. Other embodiments are described and claimed.

Claims

1. A method comprising:

determining in a shared cache memory if an error is present in a tag stored in an entry of a first cache memory coupled to the shared cache memory;

initiating a correction probe from the shared cache memory to the first cache memory if the error is present; and

correcting the error in error correction logic of the shared cache memory and forwarding the corrected tag and corresponding data from the shared cache memory to the first cache memory.

2. The method of claim 1, wherein determining if the error is present comprises determining a hit to an entry in the shared cache memory after a miss in the first cache memory for a corresponding entry, wherein the first cache memory and the shared cache memory are part of an inclusive cache hierarchy and the first cache memory includes a plurality of tag arrays having no error correction logic and the shared cache memory includes a plurality of tag arrays having error correction logic.

3. The method of claim 1, wherein initiating the correction probe comprises sending a correction signal from the shared cache memory to the first cache memory.

4. The method of claim 3, further comprising evicting a plurality of ways of a set in the first cache memory including the error, responsive to the correction probe.

5. The method of claim 4, further comprising identifying one of the plurality of evicted ways including the error and sending information of the corresponding way to the shared cache memory.

6. The method of claim 5, further comprising correcting the error in the shared cache memory and forwarding the error corrected tag and the corresponding way data to the first cache memory from the shared cache memory.

7. The method of claim 6, further comprising forwarding the error corrected tag and the corresponding way data to a processor core coupled to the first cache memory.

8. An apparatus comprising:

a first processor core including a first cache memory having a first data array and a first tag array, wherein the first tag array includes a first logic to detect an error in the first tag array but not correct the error;

a shared cache memory coupled to the first processor core, wherein the shared cache memory is inclusive with the first cache memory and other cache memories coupled to the shared cache memory, the shared cache memory including error correction logic to correct an error in the first tag array and to provide corrected tag information to replace a tag entry in the first tag array including the error.

9. The apparatus of claim 8, further comprising a second processor core including a second cache memory having a second data array and a second tag array, wherein the second tag array includes a second logic to detect an error in the second tag array but not correct the error.

10. The apparatus of claim 8, wherein the shared cache memory is to determine if an error is present in a tag stored in an entry of the first tag array and to initiate a correction probe to the first cache memory if the error is present.

11. The apparatus of claim 10, wherein the shared cache memory is to determine if the error is present when a hit occurs to an entry in the shared cache memory after a miss in the first cache memory for a corresponding entry.

12. The apparatus of claim 11, wherein the first cache memory is to evict a plurality of ways of a set including the error responsive to receipt of the correction probe and to identify one of the plurality of evicted ways including the error and send information of the corresponding way to the shared cache memory.

13. The apparatus of claim 8, wherein the first logic is to detect the error for only a matching way of the first tag array.

14. The apparatus of claim 13, wherein the first data array includes error correction logic and the first tag array does not include error correction logic.